Reverse Engineering for Beginners Dennis Yurichev cbnd ©2013-2014, Dennis Yurichev. This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License. To view a copy of this license, visit http://creativecommons.org/licenses/by-nc-nd/3.0/. Text version (May 8, 2014). There is probably a newer version of this text, and also Russian language version also accessible at http://yurichev.com/RE-book.html. E-book reader version is also available on the page. You may also subscribe to my twitter, to get information about updates of this text, etc: @yurichev1, or to subscribe to mailing list 2. 1https://twitter.com/yurichev 2http://yurichev.com/mailing_lists.html Please donate! I worked more than year on this book, here are more than 600 pages, and it’s free. Same level books has price tag from $20 to $50. More about it: 0.1. i SHORT CONTENTS SHORT CONTENTS Short contents I Code patterns 1 II Important fundamentals 312 III Finding important/interesting stu in the code 315 IV OS-specific 336 V Tools 389 VI More examples 395 VII Other things 493 VIII Books/blogs worth reading 511 IX Exercises 515 A erword 568 Appendix 570 Acronyms used 604 ii CONTENTS CONTENTS Contents 0.1 Preface............................................................. xv I Code patterns 1 1 Short introduction to the CPU 3 2 Hello, world! 4 2.1 x86...............................................................4 2.1.1 MSVC—x86......................................................4 2.1.2 GCC—x86.......................................................5 2.1.3 GCC: AT&T syntax..................................................6 2.2 x86-64.............................................................7 2.2.1 MSVC—x86-64....................................................7 2.2.2 GCC—x86-64.....................................................8 2.3 ARM..............................................................9 2.3.1 Non-optimizing Keil + ARM mode.........................................9 2.3.2 Non-optimizing Keil: thumb mode........................................ 10 2.3.3 Optimizing Xcode (LLVM) + ARM mode...................................... 11 2.3.4 Optimizing Xcode (LLVM) + thumb-2 mode................................... 11 3 Function prologue and epilogue 13 3.1 Recursion........................................................... 13 4 Stack 14 4.1 Why does the stack grow backward?........................................... 14 4.2 What is the stack used for?................................................. 15 4.2.1 Save the return address where a function must return control a er execution.............. 15 4.2.2 Passing function arguments............................................ 16 4.2.3 Local variable storage............................................... 17 4.2.4 x86: alloca() function................................................ 17 4.2.5 (Windows) SEH................................................... 19 4.2.6 Buer overflow protection............................................. 19 4.3 Typical stack layout..................................................... 19 5 printf() with several arguments 20 5.1 x86: 3 arguments....................................................... 20 5.1.1 MSVC......................................................... 20 5.1.2 MSVC and OllyDbg................................................. 21 5.1.3 GCC.......................................................... 24 5.1.4 GCC and GDB.................................................... 25 5.2 x64: 8 arguments....................................................... 27 5.2.1 MSVC......................................................... 27 5.2.2 GCC.......................................................... 28 5.2.3 GCC + GDB...................................................... 28 5.3 ARM: 3 arguments...................................................... 30 5.3.1 Non-optimizing Keil + ARM mode......................................... 30 5.3.2 Optimizing Keil + ARM mode........................................... 30 5.3.3 Optimizing Keil + thumb mode.......................................... 31 5.4 ARM: 8 arguments...................................................... 31 5.4.1 Optimizing Keil: ARM mode............................................ 31 iii CONTENTS 5.4.2 Optimizing Keil: thumb mode........................................... 32 5.4.3 Optimizing Xcode (LLVM): ARM mode...................................... 33 5.4.4 Optimizing Xcode (LLVM): thumb-2 mode.................................... 33 5.5 By the way........................................................... 34 6 scanf() 35 6.1 About pointers........................................................ 35 6.2 x86............................................................... 35 6.2.1 MSVC......................................................... 35 6.2.2 MSVC + OllyDbg................................................... 37 6.2.3 GCC.......................................................... 38 6.3 x64............................................................... 39 6.3.1 MSVC......................................................... 39 6.3.2 GCC.......................................................... 39 6.4 ARM.............................................................. 40 6.4.1 Optimizing Keil + thumb mode.......................................... 40 6.5 Global variables....................................................... 40 6.5.1 MSVC: x86...................................................... 41 6.5.2 MSVC: x86 + OllyDbg................................................ 42 6.5.3 GCC: x86....................................................... 43 6.5.4 MSVC: x64...................................................... 43 6.5.5 ARM: Optimizing Keil + thumb mode....................................... 44 6.6 scanf() result checking.................................................... 45 6.6.1 MSVC: x86...................................................... 45 6.6.2 MSVC: x86: IDA................................................... 46 6.6.3 MSVC: x86 + OllyDbg................................................ 49 6.6.4 MSVC: x86 + Hiew.................................................. 50 6.6.5 GCC: x86....................................................... 52 6.6.6 MSVC: x64...................................................... 52 6.6.7 ARM: Optimizing Keil + thumb mode....................................... 53 7 Accessing passed arguments 54 7.1 x86............................................................... 54 7.1.1 MSVC......................................................... 54 7.1.2 MSVC + OllyDbg................................................... 55 7.1.3 GCC.......................................................... 55 7.2 x64............................................................... 56 7.2.1 MSVC......................................................... 56 7.2.2 GCC.......................................................... 58 7.2.3 GCC: uint64_t instead int............................................. 59 7.3 ARM.............................................................. 59 7.3.1 Non-optimizing Keil + ARM mode......................................... 59 7.3.2 Optimizing Keil + ARM mode........................................... 60 7.3.3 Optimizing Keil + thumb mode.......................................... 60 8 One more word about results returning. 61 9 Pointers 64 9.1 Global variables example.................................................. 64 9.2 Local variables example................................................... 67 9.3 Conclusion.......................................................... 69 10 Conditional jumps 70 10.1 x86............................................................... 70 10.1.1 x86 + MSVC...................................................... 70 10.1.2 x86 + MSVC + OllyDbg............................................... 72 10.1.3 x86 + MSVC + Hiew................................................. 74 10.1.4 Non-optimizing GCC................................................ 76 10.1.5 Optimizing GCC................................................... 76 10.2 ARM.............................................................. 77 10.2.1 Optimizing Keil + ARM mode........................................... 77 10.2.2 Optimizing Keil + thumb mode.......................................... 78 iv CONTENTS 11 switch()/case/default 80 11.1 Few number of cases.................................................... 80 11.1.1 x86.......................................................... 80 11.1.2 ARM: Optimizing Keil + ARM mode........................................ 82 11.1.3 ARM: Optimizing Keil + thumb mode....................................... 82 11.2 A lot of cases......................................................... 83 11.2.1 x86.......................................................... 83 11.2.2 ARM: Optimizing Keil + ARM mode........................................ 86 11.2.3 ARM: Optimizing Keil + thumb mode....................................... 87 12 Loops 89 12.1 x86............................................................... 89 12.1.1 OllyDbg........................................................ 92 12.1.2 tracer......................................................... 93 12.2 ARM.............................................................. 95 12.2.1 Non-optimizing Keil + ARM mode......................................... 95 12.2.2 Optimizing Keil + thumb mode.......................................... 95 12.2.3 Optimizing Xcode (LLVM) + thumb-2 mode................................... 95 12.3 One more thing........................................................ 96 13 strlen() 97 13.1 x86............................................................... 97 13.1.1 Non-optimizing MSVC............................................... 97 13.1.2 Non-optimizing GCC................................................ 98 13.1.3 Optimizing MSVC.................................................. 99 13.1.4 Optimizing MSVC + OllyDbg............................................ 99 13.1.5 Optimizing GCC................................................... 101 13.2 ARM.............................................................. 102 13.2.1 Non-optimizing Xcode (LLVM) + ARM mode................................... 102 13.2.2 Optimizing Xcode (LLVM) + thumb mode.................................... 103 13.2.3 Optimizing Keil + ARM mode........................................... 103 14 Division by 9 105 14.1 x86............................................................... 105 14.2 ARM.............................................................. 106 14.2.1 Optimizing Xcode (LLVM) + ARM mode...................................... 106 14.2.2 Optimizing Xcode (LLVM) + thumb-2 mode................................... 107 14.2.3 Non-optimizing Xcode (LLVM) and Keil...................................... 107 14.3 How it works......................................................... 107 14.4 Getting divisor........................................................ 108 14.4.1 Variant #1....................................................... 108 14.4.2 Variant #2...................................................... 109 15 Working with FPU 110 15.1 Simple example....................................................... 110 15.1.1 x86.......................................................... 111 15.1.2 ARM: Optimizing Xcode (LLVM) + ARM mode.................................. 112 15.1.3 ARM: Optimizing Keil + thumb mode....................................... 113 15.2 Passing floating point number via arguments...................................... 114 15.2.1 x86.......................................................... 114 15.2.2 ARM + Non-optimizing Xcode (LLVM) + thumb-2 mode............................. 115 15.2.3 ARM + Non-optimizing Keil + ARM mode..................................... 115 15.3 Comparison example.................................................... 116 15.3.1 x86.......................................................... 116 15.3.2 Now let’s compile it with MSVC 2010 with optimization option /Ox ..................... 117 15.3.3 GCC 4.4.1....................................................... 118 15.3.4 GCC 4.4.1 with -O3 optimization turned on................................... 119 15.3.5 ARM + Optimizing Xcode (LLVM) + ARM mode.................................. 120 15.3.6 ARM + Optimizing Xcode (LLVM) + thumb-2 mode............................... 120 15.3.7 ARM + Non-optimizing Xcode (LLVM) + ARM mode............................... 122 15.3.8 ARM + Optimizing Keil + thumb mode...................................... 122 15.4 x64............................................................... 123 v CONTENTS 16 Arrays 124 16.1 Simple example....................................................... 124 16.1.1 x86.......................................................... 124 16.1.2 ARM + Non-optimizing Keil + ARM mode..................................... 126 16.1.3 ARM + Optimizing Keil + thumb mode...................................... 127 16.2 Buer overflow........................................................ 128 16.3 Buer overflow protection methods............................................ 131 16.3.1 Optimizing Xcode (LLVM) + thumb-2 mode................................... 133 16.4 One more word about arrays................................................ 135 16.5 Multidimensional arrays.................................................. 135 16.5.1 x86.......................................................... 136 16.5.2 ARM + Non-optimizing Xcode (LLVM) + thumb mode.............................. 137 16.5.3 ARM + Optimizing Xcode (LLVM) + thumb mode................................ 137 17 Bit fields 139 17.1 Specific bit checking..................................................... 139 17.1.1 x86.......................................................... 139 17.1.2 ARM.......................................................... 141 17.2 Specific bit setting/clearing................................................. 143 17.2.1 x86.......................................................... 143 17.2.2 ARM + Optimizing Keil + ARM mode....................................... 145 17.2.3 ARM + Optimizing Keil + thumb mode...................................... 145 17.2.4 ARM + Optimizing Xcode (LLVM) + ARM mode.................................. 145 17.3 Shi s.............................................................. 145 17.3.1 x86.......................................................... 146 17.3.2 ARM + Optimizing Xcode (LLVM) + ARM mode.................................. 148 17.3.3 ARM + Optimizing Xcode (LLVM) + thumb-2 mode............................... 148 17.4 CRC32 calculation example................................................. 148 18 Structures 152 18.1 SYSTEMTIME example.................................................... 152 18.2 Let’s allocate space for structure using malloc()..................................... 154 18.3 struct tm............................................................ 156 18.3.1 Linux......................................................... 156 18.3.2 ARM + Optimizing Keil + thumb mode...................................... 159 18.3.3 ARM + Optimizing Xcode (LLVM) + thumb-2 mode............................... 160 18.4 Fields packing in structure................................................. 161 18.4.1 x86.......................................................... 161 18.4.2 ARM + Optimizing Keil + thumb mode...................................... 163 18.4.3 ARM + Optimizing Xcode (LLVM) + thumb-2 mode............................... 164 18.5 Nested structures...................................................... 164 18.6 Bit fields in structure..................................................... 165 18.6.1 CPUID example................................................... 165 18.6.2 Working with the float type as with a structure................................. 168 19 Unions 172 19.1 Pseudo-random number generator example....................................... 172 20 Pointers to functions 175 20.1 MSVC.............................................................. 176 20.1.1 MSVC + OllyDbg................................................... 177 20.1.2 MSVC + tracer.................................................... 178 20.1.3 MSVC + tracer (code coverage).......................................... 179 20.2 GCC............................................................... 180 20.2.1 GCC + GDB (with source code)........................................... 181 20.2.2 GCC + GDB (no source code)............................................ 182 21 64-bit values in 32-bit environment 185 21.1 Arguments passing, addition, subtraction........................................ 185 21.2 Multiplication, division................................................... 186 21.3 Shi ing right......................................................... 188 21.4 Converting of 32-bit value into 64-bit one........................................ 189 vi CONTENTS 22 SIMD 191 22.1 Vectorization......................................................... 191 22.1.1 Intel C++....................................................... 192 22.1.2 GCC.......................................................... 195 22.2 SIMD strlen() implementation.............................................. 197 23 64 bits 201 23.1 x86-64............................................................. 201 23.2 ARM.............................................................. 208 23.3 Float point numbers..................................................... 208 24 Working with float point numbers using SIMD in x64 209 24.1 Simple example....................................................... 209 24.2 Passing floating point number via arguments...................................... 210 24.3 Comparison example.................................................... 211 24.4 Summary........................................................... 212 25 Temperature converting 213 25.1 Integer values......................................................... 213 25.1.1 MSVC 2012 x86 /Ox................................................. 213 25.1.2 MSVC 2012 x64 /Ox................................................. 215 25.2 Float point values...................................................... 215 26 C99 restrict 218 27 Inline functions 221 28 Incorrectly disassembled code 224 28.1 Disassembling started incorrectly (x86).......................................... 224 28.2 How random noise looks disassembled?......................................... 225 28.3 Information entropy of average code........................................... 241 28.3.1 x86.......................................................... 241 28.3.2 ARM (Thumb).................................................... 241 28.3.3 ARM (ARM mode).................................................. 241 28.3.4 MIPS (little endian)................................................. 242 29 C++ 243 29.1 Classes............................................................. 243 29.1.1 Simple example................................................... 243 29.1.2 Class inheritance.................................................. 249 29.1.3 Encapsulation.................................................... 252 29.1.4 Multiple inheritance................................................ 254 29.1.5 Virtual methods................................................... 257 29.2 ostream............................................................ 260 29.3 References.......................................................... 261 29.4 STL............................................................... 261 29.4.1 std::string...................................................... 261 29.4.2 std::list........................................................ 268 29.4.3 std::vector...................................................... 278 29.4.4 std::map and std::set................................................ 286 30 Obfuscation 297 30.1 Text strings.......................................................... 297 30.2 Executable code....................................................... 298 30.2.1 Inserting garbage.................................................. 298 30.2.2 Replacing instructions to bloated equivalents................................. 298 30.2.3 Always executed/never executed code...................................... 298 30.2.4 Making a lot of mess................................................ 298 30.2.5 Using indirect pointers............................................... 299 30.3 Virtual machine / pseudo-code............................................... 299 30.4 Other thing to mention................................................... 299 vii CONTENTS 31 Windows 16-bit 300 31.1 Example#1........................................................... 300 31.2 Example #2.......................................................... 300 31.3 Example #3.......................................................... 301 31.4 Example #4.......................................................... 302 31.5 Example #5.......................................................... 305 31.6 Example #6.......................................................... 309 31.6.1 Global variables................................................... 310 II Important fundamentals 312 32 Signed number representations 313 32.1 Integer overflow....................................................... 313 33 Endianness 314 33.1 Big-endian.......................................................... 314 33.2 Little-endian......................................................... 314 33.3 Bi-endian........................................................... 314 33.4 Converting data....................................................... 314 III Finding important/interesting stu in the code 315 34 Identification of executable files 317 34.1 Microso Visual C++..................................................... 317 34.1.1 Name mangling................................................... 317 34.2 GCC............................................................... 317 34.2.1 Name mangling................................................... 317 34.2.2 Cygwin........................................................ 317 34.2.3 MinGW........................................................ 317 34.3 Intel FORTRAN........................................................ 317 34.4 Watcom, OpenWatcom................................................... 318 34.4.1 Name mangling................................................... 318 34.5 Borland............................................................ 318 34.5.1 Delphi........................................................ 318 34.6 Other known DLLs...................................................... 319 35 Communication with the outer world (win32) 320 35.1 O en used functions in Windows API........................................... 320 35.2 tracer: Intercepting all functions in specific module................................... 321 36 Strings 322 36.1 Text strings.......................................................... 322 36.1.1 Unicode....................................................... 323 36.2 Error/debug messages.................................................... 325 37 Calls to assert() 326 38 Constants 327 38.1 Magic numbers........................................................ 327 38.1.1 DHCP......................................................... 328 38.2 Constant searching..................................................... 328 39 Finding the right instructions 329 40 Suspicious code patterns 331 40.1 XOR instructions....................................................... 331 40.2 Hand-written assembly code................................................ 331 41 Using magic numbers while tracing 333 42 Other things 334 viii CONTENTS 43 Old-school techniques, nevertheless, interesting to know 335 43.1 Memory “snapshots” comparing.............................................. 335 43.1.1 Windows registry.................................................. 335 IV OS-specific 336 44 Arguments passing methods (calling conventions) 337 44.1 cdecl.............................................................. 337 44.2 stdcall............................................................. 337 44.2.1 Variable arguments number functions...................................... 338 44.3 fastcall............................................................. 338 44.3.1 GCC regparm.................................................... 339 44.3.2 Watcom/OpenWatcom............................................... 339 44.4 thiscall............................................................. 339 44.5 x86-64............................................................. 339 44.5.1 Windows x64.................................................... 339 44.5.2 Linux x64....................................................... 342 44.6 Returning values of float and double type........................................ 342 44.7 Modifying arguments.................................................... 342 45 Thread Local Storage 344 46 System calls (syscall-s) 345 46.1 Linux.............................................................. 345 46.2 Windows............................................................ 346 47 Linux 347 47.1 Position-independent code................................................. 347 47.1.1 Windows....................................................... 349 47.2 LD_PRELOAD hack in Linux................................................. 349 48 Windows NT 353 48.1 CRT (win32).......................................................... 353 48.2 Win32 PE........................................................... 356 48.2.1 Terminology..................................................... 356 48.2.2 Base address.................................................... 357 48.2.3 Subsystem...................................................... 357 48.2.4 OS version...................................................... 357 48.2.5 Sections....................................................... 357 48.2.6 Relocations (relocs)................................................. 358 48.2.7 Exports and imports................................................ 359 48.2.8 Resources...................................................... 361 48.2.9 .NET.......................................................... 361 48.2.10 TLS.......................................................... 362 48.2.11 Tools......................................................... 362 48.2.12 Further reading................................................... 362 48.3 Windows SEH......................................................... 362 48.3.1 Let’s forget about MSVC.............................................. 362 48.3.2 Now let’s get back to MSVC............................................ 368 48.3.3 Windows x64.................................................... 383 48.3.4 Read more about SEH............................................... 387 48.4 Windows NT: Critical section................................................ 387 V Tools 389 49 Disassembler 390 49.1 IDA............................................................... 390 ix CONTENTS 50 Debugger 391 50.1 tracer............................................................. 391 50.2 OllyDbg............................................................ 391 50.3 GDB.............................................................. 391 51 System calls tracing 392 51.0.1 strace / dtruss.................................................... 392 52 Decompilers 393 53 Other tools 394 VI More examples 395 54 Hand decompiling + using Z3 SMT solver for defeating amateur cryptography 396 54.1 Hand decompiling...................................................... 396 54.2 Now let’s use Z3 SMT solver................................................. 400 55 Dongles 405 55.1 Example #1: MacOS Classic and PowerPC......................................... 405 55.2 Example #2: SCO OpenServer............................................... 412 55.2.1 Decrypting error messages............................................ 420 55.3 Example #3: MS-DOS..................................................... 423 56 “QR9”: Rubik’s cube inspired amateur crypto-algorithm 429 57 SAP 459 57.1 About SAP client network traic compression...................................... 459 57.2 SAP 6.0 password checking functions........................................... 470 58 Oracle RDBMS 474 58.1 V$VERSION table in the Oracle RDBMS.......................................... 474 58.2 X$KSMLRU table in Oracle RDBMS............................................. 482 58.3 V$TIMER table in Oracle RDBMS.............................................. 483 59 Handwritten assembly code 488 59.1 EICAR test file........................................................ 488 60 Demos 490 60.1 10 PRINT CHR$(205.5+RND(1)); : GOTO 10......................................... 490 60.1.1 Trixter’s 42 byte version.............................................. 490 60.1.2 My attempt to reduce Trixter’s version: 27 bytes................................ 491 60.1.3 Take a random memory garbage as a source of randomness......................... 491 60.1.4 Conclusion...................................................... 492 VII Other things 493 61 npad 494 62 Executable files patching 496 62.1 Text strings.......................................................... 496 62.2 x86 code............................................................ 496 63 Compiler intrinsic 497 64 Compiler’s anomalies 498 65 OpenMP 499 65.1 MSVC.............................................................. 501 65.2 GCC............................................................... 503 66 Itanium 505 x CONTENTS 67 8086 memory model 508 68 Basic blocks reordering 509 68.1 Profile-guided optimization................................................ 509 VIII Books/blogs worth reading 511 69 Books 512 69.1 Windows............................................................ 512 69.2 C/C++............................................................. 512 69.3 x86 / x86-64.......................................................... 512 69.4 ARM.............................................................. 512 70 Blogs 513 70.1 Windows............................................................ 513 71 Other 514 IX Exercises 515 72 Level 1 517 72.1 Exercise 1.1.......................................................... 517 72.1.1 MSVC 2012 x64 + /Ox ................................................ 517 72.1.2 Keil (ARM)...................................................... 517 72.1.3 Keil (thumb)..................................................... 517 72.2 Exercise 1.2.......................................................... 517 72.3 Exercise 1.3.......................................................... 517 72.4 Exercise 1.4.......................................................... 518 73 Level 2 519 73.1 Exercise 2.1.......................................................... 519 73.1.1 MSVC 2010...................................................... 519 73.1.2 GCC 4.4.1 + -O3 ................................................... 519 73.1.3 Keil (ARM) + -O3 ................................................... 520 73.1.4 Keil (thumb) + -O3 ................................................. 520 73.2 Exercise 2.2.......................................................... 520 73.2.1 MSVC 2010 + /Ox .................................................. 520 73.2.2 GCC 4.4.1....................................................... 521 73.2.3 Keil (ARM) + -O3 ................................................... 523 73.2.4 Keil (thumb) + -O3 ................................................. 523 73.3 Exercise 2.3.......................................................... 524 73.3.1 MSVC 2010 + /Ox .................................................. 524 73.3.2 GCC 4.4.1....................................................... 525 73.3.3 Keil (ARM) + -O3 ................................................... 525 73.3.4 Keil (thumb) + -O3 ................................................. 526 73.4 Exercise 2.4.......................................................... 526 73.4.1 MSVC 2010 + /Ox .................................................. 526 73.4.2 GCC 4.4.1....................................................... 527 73.4.3 Keil (ARM) + -O3 ................................................... 528 73.4.4 Keil (thumb) + -O3 ................................................. 529 73.5 Exercise 2.5.......................................................... 530 73.5.1 MSVC 2010 + /Ox .................................................. 530 73.6 Exercise 2.6.......................................................... 530 73.6.1 MSVC 2010 + /Ox .................................................. 530 73.6.2 Keil (ARM) + -O3 ................................................... 532 73.6.3 Keil (thumb) + -O3 ................................................. 532 73.7 Exercise 2.7.......................................................... 533 73.7.1 MSVC 2010 + /Ox .................................................. 533 73.7.2 Keil (ARM) + -O3 ................................................... 534 73.7.3 Keil (thumb) + -O3 ................................................. 536 xi CONTENTS 73.8 Exercise 2.8.......................................................... 537 73.8.1 MSVC 2010 + /O1 .................................................. 537 73.8.2 Keil (ARM) + -O3 ................................................... 538 73.8.3 Keil (thumb) + -O3 ................................................. 538 73.9 Exercise 2.9.......................................................... 539 73.9.1 MSVC 2010 + /O1 .................................................. 539 73.9.2 Keil (ARM) + -O3 ................................................... 540 73.9.3 Keil (thumb) + -O3 ................................................. 540 73.10 Exercise 2.10......................................................... 541 73.11 Exercise 2.11.......................................................... 542 73.12 Exercise 2.12.......................................................... 542 73.12.1 MSVC 2012 x64 + /Ox ................................................ 542 73.12.2 Keil (ARM)...................................................... 543 73.12.3 Keil (thumb)..................................................... 544 73.13 Exercise 2.13.......................................................... 544 73.13.1 MSVC 2012 + /Ox .................................................. 545 73.13.2 Keil (ARM)...................................................... 545 73.13.3 Keil (thumb)..................................................... 545 73.14 Exercise 2.14......................................................... 545 73.14.1 MSVC 2012...................................................... 545 73.14.2 Keil (ARM mode)................................................... 546 73.14.3 GCC 4.6.3 for Raspberry Pi (ARM mode)..................................... 547 73.15 Exercise 2.15.......................................................... 548 73.15.1 MSVC 2012 x64 /Ox................................................. 548 73.15.2 GCC 4.4.6 -O3 x64.................................................. 551 73.15.3 GCC 4.8.1 -O3 x86.................................................. 552 73.15.4 Keil (ARM mode): Cortex-R4F CPU as target................................... 553 73.16 Exercise 2.16......................................................... 554 73.16.1 MSVC 2012 x64 /Ox................................................. 554 73.16.2 Keil (ARM) -O3.................................................... 554 73.16.3 Keil (thumb) -O3................................................... 555 73.17 Exercise 2.17.......................................................... 555 73.18 Exercise 2.18......................................................... 555 73.19 Exercise 2.19......................................................... 556 74 Level 3 557 74.1 Exercise 3.1.......................................................... 557 74.2 Exercise 3.2.......................................................... 563 74.3 Exercise 3.3.......................................................... 564 74.4 Exercise 3.4.......................................................... 564 74.5 Exercise 3.5.......................................................... 564 74.6 Exercise 3.6.......................................................... 564 74.7 Exercise 3.7.......................................................... 564 74.8 Exercise 3.8.......................................................... 565 75 crackme / keygenme 566 A erword 568 76 Questions? 568 Appendix 570 A Common terminology 570 xii CONTENTS B x86 571 B.1 Terminology......................................................... 571 B.2 General purpose registers.................................................. 571 B.2.1 RAX/EAX/AX/AL................................................... 571 B.2.2 RBX/EBX/BX/BL................................................... 571 B.2.3 RCX/ECX/CX/CL................................................... 572 B.2.4 RDX/EDX/DX/DL................................................... 572 B.2.5 RSI/ESI/SI/SIL.................................................... 572 B.2.6 RDI/EDI/DI/DIL.................................................... 572 B.2.7 R8/R8D/R8W/R8L.................................................. 572 B.2.8 R9/R9D/R9W/R9L.................................................. 572 B.2.9 R10/R10D/R10W/R10L................................................ 572 B.2.10 R11/R11D/R11W/R11L................................................. 573 B.2.11 R12/R12D/R12W/R12L................................................ 573 B.2.12 R13/R13D/R13W/R13L................................................ 573 B.2.13 R14/R14D/R14W/R14L................................................ 573 B.2.14 R15/R15D/R15W/R15L................................................ 573 B.2.15 RSP/ESP/SP/SPL................................................... 573 B.2.16 RBP/EBP/BP/BPL.................................................. 573 B.2.17 RIP/EIP/IP...................................................... 574 B.2.18 CS/DS/ES/SS/FS/GS................................................ 574 B.2.19 Flags register.................................................... 574 B.3 FPU-registers......................................................... 575 B.3.1 Control Word.................................................... 575 B.3.2 Status Word..................................................... 575 B.3.3 Tag Word....................................................... 576 B.4 SIMD-registers........................................................ 576 B.4.1 MMX-registers.................................................... 576 B.4.2 SSE and AVX-registers............................................... 576 B.5 Debugging registers..................................................... 576 B.5.1 DR6.......................................................... 576 B.5.2 DR7.......................................................... 577 B.6 Instructions.......................................................... 577 B.6.1 Prefixes........................................................ 578 B.6.2 Most frequently used instructions........................................ 578 B.6.3 Less frequently used instructions......................................... 582 B.6.4 FPU instructions.................................................. 586 B.6.5 SIMD instructions.................................................. 588 B.6.6 Instructions having printable ASCII opcode................................... 588 C ARM 590 C.1 Terminology......................................................... 590 C.2 General purpose registers.................................................. 590 C.3 Current Program Status Register (CPSR)......................................... 591 C.4 VFP (floating point) and NEON registers......................................... 591 D Some GCC library functions 592 E Some MSVC library functions 593 F Cheatsheets 594 F.1 IDA............................................................... 594 F.2 OllyDbg............................................................ 594 F.3 MSVC.............................................................. 595 F.4 GCC............................................................... 595 F.5 GDB.............................................................. 595 xiii CONTENTS G Exercise solutions 597 G.1 Level 1............................................................. 597 G.1.1 Exercise 1.1...................................................... 597 G.1.2 Exercise 1.4...................................................... 597 G.2 Level 2............................................................. 597 G.2.1 Exercise 2.1...................................................... 597 G.2.2 Exercise 2.2..................................................... 597 G.2.3 Exercise 2.3..................................................... 598 G.2.4 Exercise 2.4..................................................... 598 G.2.5 Exercise 2.5..................................................... 599 G.2.6 Exercise 2.6..................................................... 599 G.2.7 Exercise 2.7..................................................... 599 G.2.8 Exercise 2.8..................................................... 600 G.2.9 Exercise 2.9..................................................... 601 G.2.10 Exercise 2.11..................................................... 601 G.2.11 Exercise 2.12..................................................... 601 G.2.12 Exercise 2.13..................................................... 601 G.2.13 Exercise 2.14..................................................... 601 G.2.14 Exercise 2.15..................................................... 601 G.2.15 Exercise 2.16..................................................... 601 G.2.16 Exercise 2.17..................................................... 602 G.2.17 Exercise 2.18..................................................... 602 G.2.18 Exercise 2.19..................................................... 602 G.3 Level 3............................................................. 602 G.3.1 Exercise 3.1...................................................... 602 G.3.2 Exercise 3.2..................................................... 602 G.3.3 Exercise 3.3..................................................... 602 G.3.4 Exercise 3.4..................................................... 602 G.3.5 Exercise 3.5..................................................... 602 G.3.6 Exercise 3.6..................................................... 602 G.3.7 Exercise 3.8..................................................... 602 Acronyms used 604 Bibliography 608 Glossary 610 Index 612 xiv 0.1. PREFACE CONTENTS 0.1 Preface Here are some of my notes about reverse engineering in English language for those beginners who would like to learn to understand x86 (which accounts for almost all executable so ware in the world) and ARM code created by C/C++ compilers. There are several popular meanings of the term “reverse engineering”: 1) reverse engineering of so ware: researching of compiled programs; 2) 3D model scanning and reworking in order to make a copy of it; 3) recreating DBMS3 structure. These notes are related to the first meaning. Topics discussed x86, ARM. Topics touched Oracle RDBMS (58), Itanium (66), copy-protection dongles (55), LD_PRELOAD (47.2), stack overflow, ELF4, win32 PE file for- mat (48.2), x86-64 (23.1), critical sections (48.4), syscalls (46), TLS5, position-independent code (PIC6)(47.1), profile-guided optimization (68.1), C++ STL (29.4), OpenMP (65), SEH (). Mini-FAQ7 • Q: Should one learn to understand assembly language these days? A: Yes: in order to have deeper understanding of the internals and to debug your so ware better and faster. • Q: Should one learn to write in assembly language these days? A: Unless one writes low-levelOS 8 code, probably no. • Q: But what about writing highly optimized routines? A: No, modern C/C++ compilers do this job better. • Q: Should I learn microprocessor internals? A: Modern CPU9-s are very complex. If you do not plan to write highly optimized code or if you do not work on compiler’s code generator then you may still learn internals in bare outlines. 10. At the same time, in order to understand and analyze compiled code it is enough to know only ISA11, register’s descriptions, i.e., the “outside” part of a CPU that is available to an application programmer. • Q: So why should I learn assembly language anyway? A: Mostly to better understand what is going on while debugging and for reverse engineering without source code, including, but not limited to, malware. • Q: How would I search for a reverse engineering job? A: There are hiring threads that appear from time to time on reddit devoted to RE12 (2013 Q3, 2014). Try to take a look there. 3Database management systems 4Executable file format widely used in *NIX system including Linux 5Thread Local Storage 6Position Independent Code: 47.1 7Frequently Asked Questions 8Operating System 9Central processing unit 10Very good text about it: [10] 11Instruction Set Architecture 12http://www.reddit.com/r/ReverseEngineering/ xv 0.1. PREFACE CONTENTS About the author Dennis Yurichev is an experienced reverse engineer and programmer. His CV is avail- able on his website13. Thanks Andrey “herm1t” Baranovich, Slava ”Avid” Kazakov, Stanislav ”Beaver” Bobrytskyy, Alexander Lysenko, Alexander ”Lstar” Chernenkiy, Andrew Zubinski, Vladimir Botov, Mark “Logxen” Cooper, Shell Rocket, Yuan Jochen Kang, Arnaud Patard (rtp on #debian-arm IRC), and all the folks on github.com who have contributed notes and corrections. A lot of LATEX packages were used: I would thank their authors as well. Praise for Reverse Engineering for Beginners •“It’s very well done .. and for free .. amazing.”14 Daniel Bilar, Siege Technologies, LLC. •“...excellent and free”15 Pete Finnigan, Oracle RDBMS security guru. •“... book is interesting, great job!” Michael Sikorski, author of Practical Malware Analysis: The Hands-On Guide to Dis- secting Malicious So ware. •“... my compliments for the very nice tutorial!” Herbert Bos, full professor at the Vrije Universiteit Amsterdam. •“... It is amazing and unbelievable.” Luis Rocha, CISSP / ISSAP, Technical Manager, Network & Information Security at Verizon Business. •“Thanks for the great work and your book.” Joris van de Vis, SAP Netweaver & Security specialist. Donate As it turns out, (technical) writing takes a lot of eort and work. This book is free, available freely and available in source code form 16 (LaTeX), and it will be so forever. My current plan for this book is to add lots of information about: PLANS17. If you want me to continue writing on all these topics you may consider donating. I worked more than year on this book 18, there are more than 500 pages. There are ≈ 300 TEX-files, ≈ 90 C/C++ source codes, ≈ 350 various listings. Price of other books on the same subject varies between $20 and $50 on amazon.com. Ways to donate are available on the page: http://yurichev.com/donate.html Every donor’s name will be included in the book! Donors also have a right to ask me to rearrange items in my writing plan. Why not try to publish? Because it’s technical literature which, as I believe, cannot be finished or frozen in paper state. Such technical references akin to Wikipedia or MSDN19 library. They can evolve and grow indefinitely. Someone can sit down and write everything from the begin to the end, publish it and forget about it. As it turns out, it’s not me. I have everyday thoughts like “that was written badly and can be rewritten better”, “that was a bad example, I know a better one”, “that is also a thing I can explain better and shorter”,etc. As you may see in commit history of this book’s source code, I make a lot of small changes almost every day: https://github.com/dennis714/RE-for-beginners/commits/master. 13http://yurichev.com/Dennis_Yurichev.pdf 14https://twitter.com/daniel_bilar/status/436578617221742593 15https://twitter.com/petefinnigan/status/400551705797869568 16https://github.com/dennis714/RE-for-beginners 17https://github.com/dennis714/RE-for-beginners/blob/master/PLANS 18Initial git commit from March 2013: https://github.com/dennis714/RE-for-beginners/tree/1e57ef540d827c7f7a92fcb3a4626af3e13c7ee4 19Microso Developer Network xvi 0.1. PREFACE CONTENTS So the book will probably be a “rolling release” as they say about Linux distros like Gentoo. No fixed releases (and dead- lines) at all, but continuous development. I don’t know how long it will take to write all I know. Maybe 10 years or more. Of course, it is not very convenient for readers who want something stable, but all I can oer is a ChangeLog 20 file serving as a “what’s new” section. Those who are interested may check it from time to time, or my blog/twitter 21 . Donors 6 * anonymous, 2 * Oleg Vygovsky, Daniel Bilar, James Truscott, Luis Rocha, Joris van de Vis, Richard S Shultz, Jang Minchang, Shade Atlas, Yao Xiao. About illustrations Those readers who are used to read a lot in the Internet, expects seeing illustrations at the places where they should be. It’s because there are no pages at all, only single one. It’s not possible to place illustrations in the book at the suitable context. So, in this book, illustrations can be at the end of section, and a referenceses in the text may be present, like “fig.1.1”. 20https://github.com/dennis714/RE-for-beginners/blob/master/ChangeLog 21http://blog.yurichev.com/ https://twitter.com/yurichev xvii Part I Code patterns 1 When I first learned C and then C++, I wrote small pieces of code, compiled them, and saw what was produced in the assembly language. This was easy for me. I did it many times and the relation between the C/C++ code and what the compiler produced was imprinted in my mind so deep that I can quickly understand what was in the original C code when I look at produced x86 code. Perhaps this technique may be helpful for someone else so I will try to describe some examples here. 2 CHAPTER 1. SHORT INTRODUCTION TO THE CPU Chapter 1 Short introduction to the CPU The CPU is the unit which executes all of the programs. Short glossary: Instruction : a primitive command to the CPU. Simplest examples: moving data between registers, working with memory, arithmetic primitives. As a rule, each CPU has its own instruction set architecture (ISA). Machine code : code for the CPU. Each instruction is usually encoded by several bytes. Assembly language : mnemonic code and some extensions like macros which are intended to make a programmer’s life easier. CPU register : Each CPU has a fixed set of general purpose registers (GPR1). ≈ 8 in x86, ≈ 16 in x86-64, ≈ 16 in ARM. The easiest way to understand a register is to think of it as an untyped temporary variable. Imagine you are working with a high-levelPL 2 and you have only 8 32-bit variables. A lot of things can be done using only these! What is the dierence between machine code and aPL? It is much easier for humans to use a high-levelPL like C/C++, Java, Python, etc., but it is easier for a CPU to use a much lower level of abstraction. Perhaps, it would be possible to invent a CPU which can execute high-levelPL code, but it would be much more complex. On the contrary, it is very inconvenient for humans to use assembly language due to its low-levelness. Besides, it is very hard to do it without making a huge amount of annoying mistakes. The program which converts high-levelPL code into assembly is called a compiler. 1General Purpose Registers 2Programming language 3 CHAPTER 2. HELLO, WORLD! Chapter 2 Hello, world! Let’s start with the famous example from the book “The C programming Language” [17]: #include int main() { printf("hello, world"); return 0; }; 2.1 x86 2.1.1 MSVC—x86 Let’s compile it in MSVC 2010: cl 1.cpp /Fa1.asm (/Fa option means generate assembly listing file) Listing 2.1: MSVC 2010 CONST SEGMENT $SG3830 DB ’hello, world’, 00H CONST ENDS PUBLIC _main EXTRN _printf:PROC ; Function compile flags: /Odtp _TEXT SEGMENT _main PROC push ebp mov ebp, esp push OFFSET $SG3830 call _printf add esp, 4 xor eax, eax pop ebp ret 0 _main ENDP _TEXT ENDS MSVC produces assembly listings in Intel-syntax. The dierence between Intel-syntax and AT&T-syntax will be discussed herea er. The compiler generated 1.obj file will be linked into 1.exe. In our case, the file contain two segments: CONST (for data constants) and _TEXT (for code). The string “hello, world” in C/C++ has type const char*, however it does not have its own name. The compiler needs to deal with the string somehow so it defines the internal name $SG3830 for it. So the example may be rewritten as: 4 2.1. X86 CHAPTER 2. HELLO, WORLD! #include const char *$SG3830="hello, world"; int main() { printf($SG3830); return 0; }; Let’s back to the assembly listing. As we can see, the string is terminated by a zero byte which is standard for C/C++ strings. More about C strings: 36.1. In the code segment, _TEXT, there is only one function so far: main(). The function main() starts with prologue code and ends with epilogue code (like almost any function) 1. A er the function prologue we see the call to the printf() function: CALL _printf. Before the call the string address (or a pointer to it) containing our greeting is placed on the stack with the help of the PUSH instruction. When the printf() function returns flow control to the main() function, string address (or pointer to it) is still in stack. Since we do not need it anymore the stack pointer (the ESP register) needs to be corrected. ADD ESP, 4 means add 4 to the value in the ESP register. Why 4? Since it is 32-bit code we need exactly 4 bytes for address passing through the stack. It is 8 bytes in x64-code. “ADD ESP, 4” is eectively equivalent to “POP register” but without using any register2. Some compilers (like Intel C++ Compiler) in the same situation may emit POP ECX instead of ADD (e.g. such a pattern can be observed in the Oracle RDBMS code as it is compiled by Intel C++ compiler). This instruction has almost the same eect but the ECX register contents will be rewritten. The Intel C++ compiler probably uses POP ECX since this instruction’s opcode is shorter then ADD ESP, x (1 byte against 3). Read more about the stack in section (4). A er the call to printf(), in the original C/C++ code was return 0 —return 0 as the result of the main() function. In the generated code this is implemented by instruction XOR EAX, EAX XOR is in fact, just “eXclusive OR” 3 but compilers o en use it instead of MOV EAX, 0 —again because it is a slightly shorter opcode (2 bytes against 5). Some compilers emit SUB EAX, EAX, which means SUBtract the value in the EAX from the value in EAX, which in any case will result zero. The last instruction RET returns control flow to the caller. Usually, it is C/C++ CRT4 code which in turn returns control to theOS. 2.1.2 GCC—x86 Now let’s try to compile the same C/C++ code in the GCC 4.4.1 compiler in Linux: gcc 1.c -o 1 Next, with the assistance of the IDA5 disassembler, let’s see how the main() function was created. (IDA, like MSVC, shows code in Intel-syntax). N.B. We could also have GCC produce assembly listings in Intel-syntax by applying the options -S -masm=intel Listing 2.2: GCC main proc near var_10 = dword ptr -10h push ebp mov ebp, esp and esp, 0FFFFFFF0h sub esp, 10h mov eax, offset aHelloWorld ; "hello, world" mov [esp+10h+var_10], eax call _printf 1Read more about it in section about function prolog and epilog (3). 2CPU flags, however, are modified 3http://en.wikipedia.org/wiki/Exclusive_or 4C runtime library: sec:CRT 5Interactive Disassembler 5 2.1. X86 CHAPTER 2. HELLO, WORLD! mov eax, 0 leave retn main endp The result is almost the same. The address of the “hello, world” string (stored in the data segment) is saved in the EAX register first and then it is stored on the stack. Also in the function prologue we see AND ESP, 0FFFFFFF0h —this instruction aligns the value in the ESP register on a 16-byte boundary. This results in all values in the stack being aligned. (The CPU performs better if the values it is dealing with are located in memory at addresses aligned on a 4- or 16-byte boundary)6. SUB ESP, 10h allocates 16 bytes on the stack. Although, as we can see herea er, only 4 are necessary here. This is because the size of the allocated stack is also aligned on a 16-byte boundary. The string address (or a pointer to the string) is then written directly onto the stack space without using the PUSH instruc- tion. var_10 —is a local variable and is also an argument for printf(). Read about it below. Then the printf() function is called. Unlike MSVC, when GCC is compiling without optimization turned on, it emits MOV EAX, 0 instead of a shorter opcode. The last instruction, LEAVE —is the equivalent of the MOV ESP, EBP and POP EBP instruction pair —in other words, this instruction sets the stack pointer( ESP) back and restores the EBP register to its initial state. This is necessary since we modified these register values (ESP and EBP) at the beginning of the function (executing MOV EBP, ESP / AND ESP, ...). 2.1.3 GCC: AT&T syntax Let’s see how this can be represented in the AT&T syntax of assembly language. This syntax is much more popular in the UNIX-world. Listing 2.3: let’s compile in GCC 4.7.3 gcc -S 1_1.c We get this: Listing 2.4: GCC 4.7.3 .file "1_1.c" .section .rodata .LC0: .string "hello, world" .text .globl main .type main, @function main: .LFB0: .cfi_startproc pushl %ebp .cfi_def_cfa_offset 8 .cfi_offset 5, -8 movl %esp, %ebp .cfi_def_cfa_register 5 andl $-16, %esp subl $16, %esp movl $.LC0, (%esp) call printf movl $0, %eax leave .cfi_restore 5 .cfi_def_cfa 4, 4 ret .cfi_endproc .LFE0: .size main, .-main .ident "GCC: (Ubuntu/Linaro 4.7.3-1ubuntu1) 4.7.3" .section .note.GNU-stack,"",@progbits 6Wikipedia: Data structure alignment 6 2.2. X86-64 CHAPTER 2. HELLO, WORLD! There are a lot of macros (beginning with dot). These are not very interesting to us so far. For now, for the sake of sim- plification, we can ignore them (except the .string macro which encodes a null-terminated character sequence just like a C-string). Then we’ll see this 7: Listing 2.5: GCC 4.7.3 .LC0: .string "hello, world" main: pushl %ebp movl %esp, %ebp andl $-16, %esp subl $16, %esp movl $.LC0, (%esp) call printf movl $0, %eax leave ret Some of the major dierences between Intel and AT&T syntax are: • Operands are written backwards. In Intel-syntax: . In AT&T syntax: . Here is a way to think about them: when you deal with Intel-syntax, you can put in equality sign (=) in your mind between operands and when you deal with AT&T-syntax put in a right arrow (→) 8. • AT&T: Before register names a percent sign must be written (%) and before numbers a dollar sign ($). Parentheses are used instead of brackets. • AT&T: A special symbol is to be added to each instruction defining the type of data: – l — long (32 bits) – w — word (16 bits) – b — byte (8 bits) Let’s go back to the compiled result: it is identical to what we saw in IDA. With one subtle dierence: 0FFFFFFF0h is written as $-16. It is the same: 16 in the decimal system is 0x10 in hexadecimal. -0x10 is equal to 0xFFFFFFF0 (for a 32-bit data type). One more thing: the return value is to be set to 0 by using usual MOV, not XOR. MOV just loads value to a register. Its name is not intuitive (data is not moved). In other architectures, this instruction has the name “load” or something like that. 2.2 x86-64 2.2.1 MSVC—x86-64 Let’s also try 64-bit MSVC: Listing 2.6: MSVC 2012 x64 $SG2989 DB ’hello, world’, 00H main PROC sub rsp, 40 lea rcx, OFFSET FLAT:$SG2923 call printf xor eax, eax add rsp, 40 ret 0 main ENDP 7This GCC option can be used to eliminate “unnecessary” macros: -fno-asynchronous-unwind-tables 8 By the way, in some C standard functions (e.g., memcpy(), strcpy()) arguments are listed in the same way as in Intel-syntax: pointer to destination memory block at the beginning and then pointer to source memory block. 7 2.2. X86-64 CHAPTER 2. HELLO, WORLD! As of x86-64, all registers were extended to 64-bit and now have a R- prefix. In order to use the stack less o en (in other words, to access external memory less o en), there exists a popular way to pass function arguments via registers (fastcall: 44.3). I.e., one part of function arguments are passed in registers, other part—via stack. In Win64, 4 function arguments are passed in RCX, RDX, R8, R9 registers. That is what we see here: a pointer to the string for printf() is now passed not in stack, but in the RCX register. Pointers are 64-bit now, so they are passed in the 64-bit part of registers (which have the R- prefix). But for backward compatibility, it is still possible to access 32-bit parts, using the E- prefix. This is how RAX/EAX/AX/AL looks like in 64-bit x86-compatible CPUs: 7th (byte number) 6th 5th 4th 3rd 2nd 1st 0th RAXx64 EAX AX AH AL The main() function returns an int-typed value, which is, in the CPL, for better backward compatibility and portability, still 32-bit, so that is why the EAX register is cleared at the function end (i.e., 32-bit part of register) instead of RAX. 2.2.2 GCC—x86-64 Let’s also try GCC in 64-bit Linux: Listing 2.7: GCC 4.4.6 x64 .string "hello, world" main: sub rsp, 8 mov edi, OFFSET FLAT:.LC0 ; "hello, world" xor eax, eax ; number of vector registers passed call printf xor eax, eax add rsp, 8 ret A method to pass function arguments in registers is also used in Linux, *BSD and Mac OS X [21]. The first 6 arguments are passed in the RDI, RSI, RDX, RCX, R8, R9 registers, and others—via stack. So the pointer to the string is passed in EDI (32-bit part of register). But why not use the 64-bit part, RDI? It is important to keep in mind that all MOV instructions in 64-bit mode writing something into the lower 32-bit register part, also clear the higher 32-bits [14]. I.e., the MOV EAX, 011223344h will write a value correctly into RAX, since the higher bits will be cleared. If we open the compiled object file (.o), we will also see all instruction’s opcodes 9: Listing 2.8: GCC 4.4.6 x64 .text:00000000004004D0 main proc near .text:00000000004004D0 48 83 EC 08 sub rsp, 8 .text:00000000004004D4 BF E8 05 40 00 mov edi, offset format ; "hello, world" .text:00000000004004D9 31 C0 xor eax, eax .text:00000000004004DB E8 D8 FE FF FF call _printf .text:00000000004004E0 31 C0 xor eax, eax .text:00000000004004E2 48 83 C4 08 add rsp, 8 .text:00000000004004E6 C3 retn .text:00000000004004E6 main endp As we can see, the instruction writing into EDI at 0x4004D4 occupies 5 bytes. The same instruction writing a 64-bit value into RDI will occupy 7 bytes. Apparently, GCC is trying to save some space. Besides, it can be sure that the data segment containing the string will not be allocated at the addresses higher than 4GiB. We also see EAX register clearance before printf() function call. This is done because a number of used vector registers is passed in EAX by standard: “with variable arguments passes information about the number of vector registers used” [21]. 9This should be enabled in Options → Disassembly → Number of opcode bytes 8 2.3. ARM CHAPTER 2. HELLO, WORLD! 2.3 ARM For my experiments with ARM processors I chose two compilers: popular in the embedded area Keil Release 6/2013 and Ap- ple Xcode 4.6.3 IDE (with LLVM-GCC 4.2 compiler), which produces code for ARM-compatible processors and SOC10 in iPod/i- Phone/iPad, Windows 8 and Window RT tables11 and also such devices as Raspberry Pi. 32-bit ARM code is used in all cases in this book, if not mentioned otherwise. 2.3.1 Non-optimizing Keil + ARM mode Let’s start by compiling our example in Keil: armcc.exe --arm --c90 -O0 1.c The armcc compiler produces assembly listings in Intel-syntax but it has high-level ARM-processor related macros12, but it is more important for us to see the instructions “as is” so let’s see the compiled result in IDA. Listing 2.9: Non-optimizing Keil + ARM mode + IDA .text:00000000 main .text:00000000 10 40 2D E9 STMFD SP!, {R4,LR} .text:00000004 1E 0E 8F E2 ADR R0, aHelloWorld ; "hello, world" .text:00000008 15 19 00 EB BL __2printf .text:0000000C 00 00 A0 E3 MOV R0, #0 .text:00000010 10 80 BD E8 LDMFD SP!, {R4,PC} .text:000001EC 68 65 6C 6C+aHelloWorld DCB "hello, world",0 ; DATA XREF: main+4 Here are a couple of ARM-related facts that we should know in order to proceed. An ARM processor has at least two major modes: ARM mode and thumb mode. In the first (ARM) mode, all instructions are enabled and each is 32 bits (4 bytes) in size. In the second (thumb) mode each instruction is 16 bits (2 bytes) in size 13. Thumb mode may look attractive because programs that use it may 1) be compact and 2) execute faster on microcontrollers having a 16-bit memory datapath. Nothing comes for free. In thumb mode, there is a reduced instruction set, only 8 registers are accessible and one needs several thumb instructions for doing some operations when you only need one in ARM mode. Starting from ARMv7 the thumb-2 instruction set is also available. This is an extended thumb mode that supports a much larger instruction set. There is a common misconception that thumb-2 is a mix of ARM and thumb. This is not correct. Rather, thumb-2 was extended to fully support processor features so it could compete with ARM mode. A program for the ARM pro- cessor may be a mix of procedures compiled for both modes. The majority of iPod/iPhone/iPad applications are compiled for the thumb-2 instruction set because Xcode does this by default. In the example we can easily see each instruction has a size of 4 bytes. Indeed, we compiled our code for ARM mode, not for thumb. The very first instruction, “STMFD SP!, {R4,LR}”14, works as an x86 PUSH instruction, writing the values of two registers (R4 andLR 15) into the stack. Indeed, in the output listing from the armcc compiler, for the sake of simplification, actually shows the “PUSH {r4,lr}” instruction. But it is not quite correct. The PUSH instruction is only available in thumb mode. So, to make things less messy, that is why I suggested working in IDA. This instruction first decrementsSP 16 so it will point to the place in the stack that is free for new entries, then it writes the values of the R4 andLR registers at the address in changedSP. This instruction (like the PUSH instruction in thumb mode) is able to save several register values at once and this may be useful. By the way, there is no such thing in x86. It can also be noted that the STMFD instruction is a generalization of the PUSH instruction (extending its features), since it can work with any register, not just withSP, and this can be very useful. The “ADR R0, aHelloWorld” instruction adds the value in thePC 17 register to the oset where the “hello, world” string is located. How is the PC register used here, one might ask? This is so-called “position-independent code”. 18 It is intended to be executed at a non-fixed address in memory. In the opcode of the ADR instruction, the dierence between the address of this instruction and the place where the string is located is encoded. The dierence will always be the same, independent of 10System on Chip 11http://en.wikipedia.org/wiki/List_of_Windows_8_and_RT_tablet_devices 12e.g. ARM mode lacks PUSH/POP instructions 13By the way, fixed-length instructions are handy in a way that one can calculate the next (or previous) instruction’s address without eort. This feature will be discussed in switch() (11.2.2) section. 14Store Multiple Full Descending 15Link Register 16stack pointer. SP/ESP/RSP in x86/x64. SP in ARM. 17Program Counter. IP/EIP/RIP in x86/64. PC in ARM. 18Read more about it in relevant section (47.1) 9 2.3. ARM CHAPTER 2. HELLO, WORLD! the address where the code is loaded by theOS. That’s why all we need is to add the address of the current instruction (from PC) in order to get the absolute address of our C-string in memory. “BL __2printf”19 instruction calls the printf() function. Here’s how this instruction works: • write the address following the BL instruction (0xC) into theLR; • then pass control flow into printf() by writing its address into thePC register. When printf() finishes its work it must have information about where it must return control. That’s why each function passes control to the address stored in theLR register. That is the dierence between “pure” RISC20-processors like ARM and CISC21-processors like x86, where the return address is stored on the stack22. By the way, an absolute 32-bit address or oset cannot be encoded in the 32-bit BL instruction because it only has space for 24 bits. It is also worth noting all ARM-mode instructions have a size of 4 bytes (32 bits). Hence they can only be located on 4-byte boundary addresses. This means the the last 2 bits of the instruction address (which are always zero bits) may be omitted. In summary, we have 26 bits for oset encoding. This is enough to represent oset ± ≈ 32푀. Next, the “MOV R0, #0”23 instruction just writes 0 into the R0 register. That’s because our C-function returns 0 and the return value is to be placed in the R0 register. The last instruction “LDMFD SP!, R4,PC”24 is an inverse instruction of STMFD. It loads values from the stack in order to save them into R4 andPC, and increments the stack pointerSP. It can be said that it is similar to POP. N.B. The very first instruction STMFD saves the R4 andLR registers pair on the stack, but R4 andPC are restored during execution of LDMFD. As I wrote before, the address of the place to where each function must return control is usually saved in theLR register. The very first function saves its value in the stack because our main() function will use the register in order to call printf(). In the function end this value can be written to thePC register, thus passing control to where our function was called. Since our main() function is usually the primary function in C/C++, control will be returned to theOS loader or to a point in CRT, or something like that. DCB is an assembly language directive defining an array of bytes or ASCII strings, akin to the DB directive in x86-assembly language. 2.3.2 Non-optimizing Keil: thumb mode Let’s compile the same example using Keil in thumb mode: armcc.exe --thumb --c90 -O0 1.c We will get (in IDA): Listing 2.10: Non-optimizing Keil + thumb mode + IDA .text:00000000 main .text:00000000 10 B5 PUSH {R4,LR} .text:00000002 C0 A0 ADR R0, aHelloWorld ; "hello, world" .text:00000004 06 F0 2E F9 BL __2printf .text:00000008 00 20 MOVS R0, #0 .text:0000000A 10 BD POP {R4,PC} .text:00000304 68 65 6C 6C+aHelloWorld DCB "hello, world",0 ; DATA XREF: main+2 We can easily spot the 2-byte (16-bit) opcodes. This is, as I mentioned, thumb. The BL instruction however consists of two 16-bit instructions. This is because it is impossible to load an oset for the printf() function intoPC while using the small space in one 16-bit opcode. That’s why the first 16-bit instruction loads the higher 10 bits of the oset and the second instruction loads the lower 11 bits of the oset. As I mentioned, all instructions in thumb mode have a size of 2 bytes (or 16 bits). This means it is impossible for a thumb-instruction to be at an odd address whatsoever. Given the above, the last address bit may be omitted while encoding instructions. In summary, in the BL thumb-instruction ± ≈ 2푀 can be encoded as the oset from the current address. As for the other instructions in the function: PUSH and POP work just like the described STMFD/LDMFD but theSP register is not mentioned explicitly here. ADR works just like in previous example. MOVS writes 0 into the R0 register in order to return zero. 19Branch with Link 20Reduced instruction set computing 21Complex instruction set computing 22Read more about this in next section (4) 23MOVe 24Load Multiple Full Descending 10 2.3. ARM CHAPTER 2. HELLO, WORLD! 2.3.3 Optimizing Xcode (LLVM) + ARM mode Xcode 4.6.3 without optimization turned on produces a lot of redundant code so we’ll study the version where the instruction count is as small as possible: -O3. Listing 2.11: Optimizing Xcode (LLVM) + ARM mode __text:000028C4 _hello_world __text:000028C4 80 40 2D E9 STMFD SP!, {R7,LR} __text:000028C8 86 06 01 E3 MOV R0, #0x1686 __text:000028CC 0D 70 A0 E1 MOV R7, SP __text:000028D0 00 00 40 E3 MOVT R0, #0 __text:000028D4 00 00 8F E0 ADD R0, PC, R0 __text:000028D8 C3 05 00 EB BL _puts __text:000028DC 00 00 A0 E3 MOV R0, #0 __text:000028E0 80 80 BD E8 LDMFD SP!, {R7,PC} __cstring:00003F62 48 65 6C 6C+aHelloWorld_0 DCB "Hello world!",0 The instructions STMFD and LDMFD are familiar to us. The MOV instruction just writes the number 0x1686 into the R0 register. This is the oset pointing to the “Hello world!” string. The R7 register as it is standardized in [2] is a frame pointer. More on it below. The MOVT R0, #0 instruction writes 0 into higher 16 bits of the register. The issue here is that the generic MOV instruction in ARM mode may write only the lower 16 bits of the register. Remember, all instruction opcodes in ARM mode are limited in size to 32 bits. Of course, this limitation is not related to moving between registers. That’s why an additional instruction MOVT exists for writing into the higher bits (from 16 to 31 inclusive). However, its usage here is redundant because the “MOV R0, #0x1686” instruction above cleared the higher part of the register. This is probably a shortcoming of the compiler. The “ADD R0, PC, R0” instruction adds the value in thePC to the value in the R0, to calculate absolute address of the “Hello world!” string. As we already know, it is “position-independent code” so this correction is essential here. The BL instruction calls the puts() function instead of printf(). GCC replaced the firstprintf()call withputs(). Indeed: printf()with a sole argument is almost analogous toputs(). Almost because we need to be sure the string will not contain printf-control statements starting with %: then the eect of these two functions would be dierent 25. Why did the compiler replace the printf() with puts()? Because puts() is faster 26. puts() works faster because it just passes characters to stdout without comparing each to the % symbol. Next, we see the familiar “MOV R0, #0”instruction intended to set the R0 register to 0. 2.3.4 Optimizing Xcode (LLVM) + thumb-2 mode By default Xcode 4.6.3 generates code for thumb-2 in this manner: Listing 2.12: Optimizing Xcode (LLVM) + thumb-2 mode __text:00002B6C _hello_world __text:00002B6C 80 B5 PUSH {R7,LR} __text:00002B6E 41 F2 D8 30 MOVW R0, #0x13D8 __text:00002B72 6F 46 MOV R7, SP __text:00002B74 C0 F2 00 00 MOVT.W R0, #0 __text:00002B78 78 44 ADD R0, PC __text:00002B7A 01 F0 38 EA BLX _puts __text:00002B7E 00 20 MOVS R0, #0 __text:00002B80 80 BD POP {R7,PC} ... __cstring:00003E70 48 65 6C 6C 6F 20+aHelloWorld DCB "Hello world!",0xA,0 The BL and BLX instructions in thumb mode, as we recall, are encoded as a pair of 16-bit instructions. In thumb-2 these surrogate opcodes are extended in such a way so that new instructions may be encoded here as 32-bit instructions. That’s easily observable —opcodes of thumb-2 instructions also begin with 0xFx or 0xEx. But in the IDA listings two opcode bytes 25It should also be noted the puts() does not require a ’\n’ new line symbol at the end of a string, so we do not see it here. 26http://www.ciselant.de/projects/gcc_printf/gcc_printf.html 11 2.3. ARM CHAPTER 2. HELLO, WORLD! are swapped (for thumb and thumb-2 modes). For instructions in ARM mode, the order is the fourth byte, then the third, then the second and finally the first (due to dierent endianness). So as we can see, the MOVW, MOVT.W and BLX instructions begin with 0xFx. One of the thumb-2 instructions is “MOVW R0, #0x13D8” —it writes a 16-bit value into the lower part of the R0 register. Also, “MOVT.W R0, #0” works just like MOVT from the previous example but it works in thumb-2. Among other dierences, here the BLX instruction is used instead of BL. The dierence is that, besides saving the RA27 in theLR register and passing control to the puts() function, the processor is also switching from thumb mode to ARM (or back). This instruction is placed here since the instruction to which control is passed looks like (it is encoded in ARM mode): __symbolstub1:00003FEC _puts ; CODE XREF: _hello_world+E __symbolstub1:00003FEC 44 F0 9F E5 LDR PC, =__imp__puts So, the observant reader may ask: why not call puts() right at the point in the code where it is needed? Because it is not very space-eicient. Almost any program uses external dynamic libraries (like DLL in Windows, .so in *NIX or .dylib in Mac OS X). O en-used library functions are stored in dynamic libraries, including the standard C-function puts(). In an executable binary file (Windows PE .exe, ELF or Mach-O) an import section is present. This is a list of symbols (func- tions or global variables) being imported from external modules along with the names of these modules. TheOS loader loads all modules it needs and, while enumerating import symbols in the primary module, determines the correct addresses of each symbol. In our case,__imp__putsis a 32-bit variable where theOS loader will write the correct address of the function in an external library. Then the LDR instruction just takes the 32-bit value from this variable and writes it into thePC register, passing control to it. So, in order to reduce the time that anOS loader needs for doing this procedure, it is good idea for it to write the address of each symbol only once to a specially-allocated place just for it. Besides, as we have already figured out, it is impossible to load a 32-bit value into a register while using only one instruc- tion without a memory access. So, it is optimal to allocate a separate function working in ARM mode with only one goal —to pass control to the dynamic library and then to jump to this short one-instruction function (the so-called thunk function) from thumb-code. By the way, in the previous example (compiled for ARM mode) control passed by the BL instruction goes to the same thunk function. However the processor mode is not switched (hence the absence of an “X” in the instruction mnemonic). 27Return Address 12 CHAPTER 3. FUNCTION PROLOGUE AND EPILOGUE Chapter 3 Function prologue and epilogue A function prologue is a sequence of instructions at the start of a function. It o en looks something like the following code fragment: push ebp mov ebp, esp sub esp, X What these instruction do: saves the value in the EBP register, sets the value of the EBP register to the value of the ESP and then allocates space on the stack for local variables. The value in the EBP is fixed over a period of function execution and it is to be used for local variables and arguments access. One can use ESP, but it is changing over time and it is not convenient. The function epilogue frees allocated space in the stack, returns the value in the EBP register back to initial state and returns the control flow to callee: mov esp, ebp pop ebp ret 0 Function prologues and epilogues are usually detected in disassemblers for function delimitation from each other. 3.1 Recursion Epilogues and prologues can make recursion performance worse. For example, once upon a time I wrote a function to seek the correct node in a binary tree. As a recursive function it would look stylish but since additional time is to be spend at each function call for the prologue/epilogue, it was working a couple of times slower than an iterative (recursion-free) implementation. By the way, that is the reason compilers use tail call. 13 CHAPTER 4. STACK Chapter 4 Stack A stack is one of the most fundamental data structures in computer science 1. Technically, it is just a block of memory in process memory along with the ESP or RSP register in x86 or x64, or theSP register in ARM, as a pointer within the block. The most frequently used stack access instructions are PUSH and POP (in both x86 and ARM thumb-mode). PUSH subtracts 4in 32-bit mode (or8in 64-bit mode) fromESP/RSP/SP and then writes the contents of its sole operand to the memory address pointed to by ESP/RSP/SP. POP is the reverse operation: get the data from memory pointed to bySP, put it in the operand (o en a register) and then add 4 (or 8) to the stack pointer. A er stack allocation the stack pointer points to the end of stack. PUSH decreases the stack pointer and POP increases it. The end of the stack is actually at the beginning of the memory allocated for the stack block. It seems strange, but that’s the way it is. Nevertheless ARM not only has instructions supporting descending stacks but also ascending stacks. For example the STMFD2/LDMFD3, STMED4/LDMED5 instructions are intended to deal with a descending stack. The STMFA6/LMDFA7, STMEA8/LDMEA9 instructions are intended to deal with an ascending stack. 4.1 Why does the stack grow backward? Intuitively, we might think that, like any other data structure, the stack may grow upward, i.e., towards higher addresses. The reason the stack grows backward is probably historical. When computers were big and occupied a whole room, it was easy to divide memory into two parts, one for the heap and one for the stack. Of course, it was unknown how big the heap and the stack would be during program execution, so this solution was the simplest possible. Heap Stack Start of heap Start of stack In [26] we can read: The user-core part of an image is divided into three logical segments. The program text segment begins at location 0 in the virtual address space. During execution, this segment is write-protected and a single copy of it is shared among all processes executing the same program. At the first 8K byte boundary above 1http://en.wikipedia.org/wiki/Call_stack 2Store Multiple Full Descending 3Load Multiple Full Descending 4Store Multiple Empty Descending 5Load Multiple Empty Descending 6Store Multiple Full Ascending 7Load Multiple Full Ascending 8Store Multiple Empty Ascending 9Load Multiple Empty Ascending 14 4.2. WHAT IS THE STACK USED FOR? CHAPTER 4. STACK the program text segment in the virtual address space begins a nonshared, writable data segment, the size of which may be extended by a system call. Starting at the highest address in the virtual address space is a stack segment, which automatically grows downward as the hardware’s stack pointer fluctuates. 4.2 What is the stack used for? 4.2.1 Save the return address where a function must return control a er execution x86 While calling another function with a CALL instruction the address of the point exactly a er the CALL instruction is saved to the stack and then an unconditional jump to the address in the CALL operand is executed. The CALL instruction is equivalent to a PUSH address_after_call / JMP operand instruction pair. RET fetches a value from the stack and jumps to it —it is equivalent to a POP tmp / JMP tmp instruction pair. Overflowing the stack is straightforward. Just run eternal recursion: void f() { f(); }; MSVC 2008 reports the problem: c:\tmp6>cl ss.cpp /Fass.asm Microsoft (R) 32-bit C/C++ Optimizing Compiler Version 15.00.21022.08 for 80x86 Copyright (C) Microsoft Corporation. All rights reserved. ss.cpp c:\tmp6\ss.cpp(4) : warning C4717: ’f’ : recursive on all control paths, function will cause ⤦ Ç runtime stack overflow ...but generates the right code anyway: ?f@@YAXXZ PROC ; f ; File c:\tmp6\ss.cpp ; Line 2 push ebp mov ebp, esp ; Line 3 call ?f@@YAXXZ ; f ; Line 4 pop ebp ret 0 ?f@@YAXXZ ENDP ; f ...Also if we turn on optimization (/Ox option) the optimized code will not overflow the stack but instead will work cor- rectly10: ?f@@YAXXZ PROC ; f ; File c:\tmp6\ss.cpp ; Line 2 $LL3@f: ; Line 3 jmp SHORT $LL3@f ?f@@YAXXZ ENDP ; f GCC 4.4.1 generates similar code in both cases, although without issuing any warning about the problem. 10irony here 15 4.2. WHAT IS THE STACK USED FOR? CHAPTER 4. STACK ARM ARM programs also use the stack for saving return addresses, but dierently. As mentioned in “Hello, world!” (2.3), the RA is saved to theLR(link register). However, if one needs to call another function and use theLR register one more time its value should be saved. Usually it is saved in the function prologue. O en, we see instructions like “PUSH R4-R7,LR” along with this instruction in epilogue “POP R4-R7,PC” —thus register values to be used in the function are saved in the stack, includingLR. Nevertheless, if a function never calls any other function, in ARM terminology it is called a leaf function11. As a conse- quence, leaf functions do not use theLR register. If this function is small and uses a small number of registers, it may not use the stack at all. Thus, it is possible to call leaf functions without using the stack. This can be faster than on x86 because external RAM is not used for the stack 12. It can be useful for such situations when memory for the stack is not yet allocated or not available. 4.2.2 Passing function arguments The most popular way to pass parameters in x86 is called “cdecl”: push arg3 push arg2 push arg1 call f add esp, 4*3 Callee functions get their arguments via the stack pointer. Consequently, this is how values will be located in the stack before execution of the very first instruction of the f() function: ESP return address ESP+4 argument#1, marked in IDA as arg_0 ESP+8 argument#2, marked in IDA as arg_4 ESP+0xC argument#3, marked in IDA as arg_8 ...... See also the section about other calling conventions (44). It is worth noting that nothing obliges programmers to pass arguments through the stack. It is not a requirement. One could implement any other method without using the stack at all. For example, it is possible to allocate a space for arguments in the heap, fill it and pass it to a function via a pointer to this block in the EAX register. This will work. 13. However, it is a convenient custom in x86 and ARM to use the stack for this. By the way, the callee function does not have any information about how many arguments were passed. Functions with a variable number of arguments (like printf()) determine the number by specifiers (which begin with a % sign) in the format string. If we write something like printf("%d %d %d", 1234); printf() will dump 1234, and then also two random numbers, which were laying near it in the stack, by chance. That’s why it is not very important how we declare the main() function: as main(), main(int argc, char *argv[]) or main(int argc, char *argv[], char *envp[]). In fact, CRT-code is calling main() roughly as: push envp push argv push argc call main ... If you declare main() as main() without arguments, they are, nevertheless, still present in the stack, but not used. If you declare main() as main(int argc, char *argv[]), you will use two arguments, and third will remain “invisible” for your function. Even more than that, it is possible to declare main(int argc), and it will work. 11http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka13785.html 12Some time ago, on PDP-11 and VAX, the CALL instruction (calling other functions) was expensive; up to 50% of execution time might be spent on it, so it was common sense that big number of small function is anti-pattern[25, Chapter 4, Part II]. 13For example, in the “The Art of Computer Programming” book by Donald Knuth, in section 1.4.1 dedicated to subroutines [18, section 1.4.1], we can read about one way to supply arguments to a subroutine is simply to list them a er the JMP instruction passing control to subroutine. Knuth writes this method was particularly convenient on System/360. 16 4.2. WHAT IS THE STACK USED FOR? CHAPTER 4. STACK 4.2.3 Local variable storage A function could allocate space in the stack for its local variables just by shi ing the stack pointer towards the stack bottom. It is also not a requirement. You could store local variables wherever you like, but traditionally this is how it’s done. 4.2.4 x86: alloca() function It is worth noting the alloca() function.14. This function works like malloc() but allocates memory just on the stack. The allocated memory chunk does not need to be freed via a free() function call since the function epilogue (3) will return ESP back to its initial state and the allocated memory will be just annulled. It is worth noting how alloca() is implemented. In simple terms, this function just shi s ESP downwards toward the stack bottom by the number of bytes you need and sets ESP as a pointer to the allocated block. Let’s try: #ifdef __GNUC__ #include // GCC #else #include // MSVC #endif #include void f() { char *buf=(char*)alloca (600); #ifdef __GNUC__ snprintf (buf, 600, "hi! %d, %d, %d\n", 1, 2, 3); // GCC #else _snprintf (buf, 600, "hi! %d, %d, %d\n", 1, 2, 3); // MSVC #endif puts (buf); }; (_snprintf() function works just like printf(), but instead of dumping the result into stdout (e.g., to terminal or con- sole), it writes to the buf buer. puts() copies buf contents to stdout. Of course, these two function calls might be replaced by one printf() call, but I would like to illustrate small buer usage.) MSVC Let’s compile (MSVC 2010): Listing 4.1: MSVC 2010 ... mov eax, 600 ; 00000258H call __alloca_probe_16 mov esi, esp push 3 push 2 push 1 push OFFSET $SG2672 push 600 ; 00000258H push esi call __snprintf push esi call _puts add esp, 28 ; 0000001cH 14In MSVC, the function implementation can be found in alloca16.asm and chkstk.asm in C:\Program Files (x86)\Microsoft Visual Studio 10.0\VC\crt\src\intel 17 4.2. WHAT IS THE STACK USED FOR? CHAPTER 4. STACK ... The sole alloca() argument is passed via EAX (instead of pushing into stack) 15. A er the alloca() call, ESP points to the block of 600 bytes and we can use it as memory for the buf array. GCC + Intel syntax GCC 4.4.1 can do the same without calling external functions: Listing 4.2: GCC 4.7.3 .LC0: .string "hi! %d, %d, %d\n" f: push ebp mov ebp, esp push ebx sub esp, 660 lea ebx, [esp+39] and ebx, -16 ; align pointer by 16-bit border mov DWORD PTR [esp], ebx ; s mov DWORD PTR [esp+20], 3 mov DWORD PTR [esp+16], 2 mov DWORD PTR [esp+12], 1 mov DWORD PTR [esp+8], OFFSET FLAT:.LC0 ; "hi! %d, %d, %d\n" mov DWORD PTR [esp+4], 600 ; maxlen call _snprintf mov DWORD PTR [esp], ebx ; s call puts mov ebx, DWORD PTR [ebp-4] leave ret GCC + AT&T syntax Let’s see the same code, but in AT&T syntax: Listing 4.3: GCC 4.7.3 .LC0: .string "hi! %d, %d, %d\n" f: pushl %ebp movl %esp, %ebp pushl %ebx subl $660, %esp leal 39(%esp), %ebx andl $-16, %ebx movl %ebx, (%esp) movl $3, 20(%esp) movl $2, 16(%esp) movl $1, 12(%esp) movl $.LC0, 8(%esp) movl $600, 4(%esp) call _snprintf movl %ebx, (%esp) call puts movl -4(%ebp), %ebx leave 15It is because alloca() is rather compiler intrinsic (63) than usual function. One of the reason there is a separate function instead of couple instructions just in the code, because MSVC16 implementation of the alloca() function also has a code which reads from the memory just allocated, in order to letOS to map physical memory to thisVM 17 region. 18 4.3. TYPICAL STACK LAYOUT CHAPTER 4. STACK ret The code is the same as in the previous listing. N.B. E.g. movl $3, 20(%esp) is analogous to mov DWORD PTR [esp+20], 3 in Intel-syntax —when addressing mem- ory in form register+oset, it is written in AT&T syntax as offset(%register). 4.2.5 (Windows) SEH SEH18 records are also stored on the stack (if they present).. Read more about it: (48.3). 4.2.6 Buer overflow protection More about it here (16.2). 4.3 Typical stack layout A very typical stack layout in a 32-bit environment at the start of a function: ...... ESP-0xC local variable #2, marked in IDA as var_8 ESP-8 local variable #1, marked in IDA as var_4 ESP-4 saved value of EBP ESP return address ESP+4 argument#1, marked in IDA as arg_0 ESP+8 argument#2, marked in IDA as arg_4 ESP+0xC argument#3, marked in IDA as arg_8 ...... 18Structured Exception Handling: 48.3 19 CHAPTER 5. PRINTF() WITH SEVERAL ARGUMENTS Chapter 5 printf() with several arguments Now let’s extend the Hello, world! (2) example, replacing printf() in the main() function body by this: #include int main() { printf("a=%d; b=%d; c=%d", 1, 2, 3); return 0; }; 5.1 x86: 3 arguments 5.1.1 MSVC Let’s compile it by MSVC 2010 Express and we got: $SG3830 DB ’a=%d; b=%d; c=%d’, 00H ... push 3 push 2 push 1 push OFFSET $SG3830 call _printf add esp, 16 ; 00000010H Almost the same, but now we can see the printf() arguments are pushed onto the stack in reverse order. The first argument is pushed last. By the way, variables of int type in 32-bit environment have 32-bit width, that is 4 bytes. So, we have here 4 arguments. 4 ∗ 4 = 16 —they occupy exactly 16 bytes in the stack: a 32-bit pointer to a string and 3 numbers of type int. When the stack pointer( ESP register) is corrected by “ADD ESP, X” instruction a er a function call, o en, the number of function arguments can be deduced here: just divide X by 4. Of course, this is related only to cdecl calling convention. See also the section about calling conventions (44). It is also possible for the compiler to merge several “ADD ESP, X” instructions into one, a er the last call: push a1 push a2 call ... ... push a1 call ... ... push a1 20 5.1. X86: 3 ARGUMENTS CHAPTER 5. PRINTF() WITH SEVERAL ARGUMENTS push a2 push a3 call ... add esp, 24 5.1.2 MSVC and OllyDbg Now let’s try to load this example in OllyDbg. It is one of the most popular user-land win32 debugger. We can try to compile our example in MSVC 2012 with /MD option, meaning, to link against MSVCR*.DLL, so we will able to see imported functions clearly in debugger. Then load executable in OllyDbg. The very first breakpoint is in ntdll.dll, press F9 (run). The second breakpoint is in CRT-code. Now we should find main() function. Find this code by scrolling the code to the very bottom (MSVC allocates main() function at the very beginning of the code section): fig. 5.3. Click on PUSH EBP instruction, press F2 (set breakpoint) and press F9 (run). We need to do these manupulations in order to skip CRT-code, because, we don’t really interesting in it yet. Press F8 (step over) 6 times, i.e., skip 6 instructions: fig. 5.4. Now thePC points to the CALL printf instruction. OllyDbg, like other debuggers, highlights value of registers which were changed. So each time you press F8, EIP is changing and its value looking red. ESP is changing as well, because values are pushed into the stack. Where are the values in the stack? Take a look into right/bottom window of debugger: Figure 5.1: OllyDbg: stack a er values pushed (I made round red mark here in graphics editor) So we can see there 3 columns: address in the stack, value in the stack and some additional OllyDbg comments. OllyDbg understands printf()-like strings, so it reports the string here and 3 values attached to it. It is possible to right-click on the format string, click on “Follow in dump”,and the format string will appear in the window at the le -bottom part, where some memory part is always seen. These memory values can be edited. It is possible to change the format string, and then the result of our example will be dierent. It is probably not very useful now, but it’s very good idea for doing it as exercise, to get feeling how everything is works here. Press F8 (step over). In the console we’ll see the output: Figure 5.2: printf() function executed Let’s see how registers and stack state are changed: fig. 5.5. EAX register now contains 0xD (13). That’s correct, printf() returns number of characters printed. EIP value is changed: indeed, now there is address of the instruction a er CALL printf. ECX and EDX values are changed as well. Apparently, printf() function’s hidden machinery used them for its own needs. A very important thing is that ESP value is not changed. And stack state too! We clearly see that format string and cor- responding 3 values are still there. Indeed, that’s cdecl calling convention, calling function doesn’t clear arguments in stack. It’s caller’s duty to do so. Press F8 again to execute ADD ESP, 10 instruction: fig. 5.6. 21 5.1. X86: 3 ARGUMENTS CHAPTER 5. PRINTF() WITH SEVERAL ARGUMENTS ESP is changed, but values are still in the stack! Yes, of course, no one needs to fill these values by zero or something like that. Because, everything above stack pointer (SP) is noise or garbage, it has no value at all. It would be time consuming to clear unused stack entries, besides, no one really needs to. Figure 5.3: OllyDbg: the very start of the main() function 22 5.1. X86: 3 ARGUMENTS CHAPTER 5. PRINTF() WITH SEVERAL ARGUMENTS Figure 5.4: OllyDbg: before printf() execution Figure 5.5: OllyDbg: a er printf() execution 23 5.1. X86: 3 ARGUMENTS CHAPTER 5. PRINTF() WITH SEVERAL ARGUMENTS Figure 5.6: OllyDbg: a er ADD ESP, 10 instruction execution 5.1.3 GCC Now let’s compile the same program in Linux using GCC 4.4.1 and take a look in IDA what we got: main proc near var_10 = dword ptr -10h var_C = dword ptr -0Ch var_8 = dword ptr -8 var_4 = dword ptr -4 push ebp mov ebp, esp and esp, 0FFFFFFF0h sub esp, 10h mov eax, offset aADBDCD ; "a=%d; b=%d; c=%d" mov [esp+10h+var_4], 3 mov [esp+10h+var_8], 2 mov [esp+10h+var_C], 1 mov [esp+10h+var_10], eax call _printf mov eax, 0 leave retn main endp It can be said that the dierence between code from MSVC and code from GCC is only in the method of placing arguments on the stack. Here GCC is working directly with the stack without PUSH/POP. 24 5.1. X86: 3 ARGUMENTS CHAPTER 5. PRINTF() WITH SEVERAL ARGUMENTS 5.1.4 GCC and GDB Let’s try this example also in GDB1 in Linux. -g mean produce debug information into executable file. $ gcc 1.c -g -o 1 $ gdb 1 GNU gdb (GDB) 7.6.1-ubuntu Copyright (C) 2013 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Type "show copying" and "show warranty" for details. This GDB was configured as "i686-linux-gnu". For bug reporting instructions, please see: : mov $0x0,%eax 0x804844f : leave 0x8048450 : ret 0x8048451: xchg %ax,%ax 0x8048453: xchg %ax,%ax Two XCHG instructions, apparently, is some random garbage, which we can ignore so far. The second element (0x080484f0) is an address of format string: (gdb) x/s 0x080484f0 0x80484f0: "a=%d; b=%d; c=%d" Other 3 elements (1, 2, 3) are printf() arguments. Other elements may be just “garbage” present in stack, but also may be values from other functions, their local variables, etc. We can ignore it yet. Execute “finish”. This mean, execute till function end. Here it means: execute till the finish of printf(). (gdb) finish Run till exit from #0 __printf (format=0x80484f0 "a=%d; b=%d; c=%d") at printf.c:29 main () at 1.c:6 6 return 0; Value returned is $2 = 13 1GNU debugger 25 5.1. X86: 3 ARGUMENTS CHAPTER 5. PRINTF() WITH SEVERAL ARGUMENTS GDB shows what printf() returned in EAX (13). This is number of characters printed, just like in the example with Olly- Dbg. We also see “return 0;” and the information that this expression is in the 1.c file at the line 6. Indeed, the 1.c file is located in the current directory, and GDB finds the string there. How GDB knows, which C-code line is being executed now? This is related to the fact that compiler, while generating debugging information, also saves a table of relations between source code line numbers and instruction addresses. GDB is source-level debugger, a er all. Let’s examine registers. 13 in EAX: (gdb) info registers eax 0xd 13 ecx 0x0 0 edx 0x0 0 ebx 0xb7fc0000 -1208221696 esp 0xbffff120 0xbffff120 ebp 0xbffff138 0xbffff138 esi 0x0 0 edi 0x0 0 eip 0x804844a 0x804844a ... Let’s disassemble current instructions. Arrow points to the instruction being executed next. (gdb) disas Dump of assembler code for function main: 0x0804841d <+0>: push %ebp 0x0804841e <+1>: mov %esp,%ebp 0x08048420 <+3>: and $0xfffffff0,%esp 0x08048423 <+6>: sub $0x10,%esp 0x08048426 <+9>: movl $0x3,0xc(%esp) 0x0804842e <+17>: movl $0x2,0x8(%esp) 0x08048436 <+25>: movl $0x1,0x4(%esp) 0x0804843e <+33>: movl $0x80484f0,(%esp) 0x08048445 <+40>: call 0x80482f0 => 0x0804844a <+45>: mov $0x0,%eax 0x0804844f <+50>: leave 0x08048450 <+51>: ret End of assembler dump. GDB shows disassembly in AT&T syntax by default. It’s possible to switch to Intel syntax: (gdb) set disassembly-flavor intel (gdb) disas Dump of assembler code for function main: 0x0804841d <+0>: push ebp 0x0804841e <+1>: mov ebp,esp 0x08048420 <+3>: and esp,0xfffffff0 0x08048423 <+6>: sub esp,0x10 0x08048426 <+9>: mov DWORD PTR [esp+0xc],0x3 0x0804842e <+17>: mov DWORD PTR [esp+0x8],0x2 0x08048436 <+25>: mov DWORD PTR [esp+0x4],0x1 0x0804843e <+33>: mov DWORD PTR [esp],0x80484f0 0x08048445 <+40>: call 0x80482f0 => 0x0804844a <+45>: mov eax,0x0 0x0804844f <+50>: leave 0x08048450 <+51>: ret End of assembler dump. Execute next instruction. GDB shows ending bracket, meaning, this is ending block of function. (gdb) step 7 }; Let’s see registers a er MOV EAX, 0 instruction execution. EAX here is zero indeed. 26 5.2. X64: 8 ARGUMENTS CHAPTER 5. PRINTF() WITH SEVERAL ARGUMENTS (gdb) info registers eax 0x0 0 ecx 0x0 0 edx 0x0 0 ebx 0xb7fc0000 -1208221696 esp 0xbffff120 0xbffff120 ebp 0xbffff138 0xbffff138 esi 0x0 0 edi 0x0 0 eip 0x804844f 0x804844f ... 5.2 x64: 8 arguments To see how other arguments will be passed via the stack, let’s change our example again by increasing the number of argu- ments to be passed to 9 (printf() format string + 8 int variables): #include int main() { printf("a=%d; b=%d; c=%d; d=%d; e=%d; f=%d; g=%d; h=%d\n", 1, 2, 3, 4, 5, 6, 7, 8); return 0; }; 5.2.1 MSVC As we saw before, the first 4 arguments are passed in the RCX, RDX, R8, R9 registers in Win64, while all the rest—via the stack. That is what we see here. However, the MOV instruction, instead of PUSH, is used for preparing the stack, so the values are written to the stack in a straightforward manner. Listing 5.2: MSVC 2012 x64 $SG2923 DB ’a=%d; b=%d; c=%d; d=%d; e=%d; f=%d; g=%d; h=%d’, 0aH, 00H main PROC sub rsp, 88 mov DWORD PTR [rsp+64], 8 mov DWORD PTR [rsp+56], 7 mov DWORD PTR [rsp+48], 6 mov DWORD PTR [rsp+40], 5 mov DWORD PTR [rsp+32], 4 mov r9d, 3 mov r8d, 2 mov edx, 1 lea rcx, OFFSET FLAT:$SG2923 call printf ; return 0 xor eax, eax add rsp, 88 ret 0 main ENDP _TEXT ENDS END 27 5.2. X64: 8 ARGUMENTS CHAPTER 5. PRINTF() WITH SEVERAL ARGUMENTS 5.2.2 GCC In *NIX OS-es, it’s the same story for x86-64, except that the first 6 arguments are passed in the RDI, RSI, RDX, RCX, R8, R9 registers. All the rest—via the stack. GCC generates the code writing string pointer into EDI instead if RDI—we saw this thing before: 2.2.2. We also saw before the EAX register being cleared before a printf() call: 2.2.2. Listing 5.3: GCC 4.4.6 -O3 x64 .LC0: .string "a=%d; b=%d; c=%d; d=%d; e=%d; f=%d; g=%d; h=%d\n" main: sub rsp, 40 mov r9d, 5 mov r8d, 4 mov ecx, 3 mov edx, 2 mov esi, 1 mov edi, OFFSET FLAT:.LC0 xor eax, eax ; number of vector registers passed mov DWORD PTR [rsp+16], 8 mov DWORD PTR [rsp+8], 7 mov DWORD PTR [rsp], 6 call printf ; return 0 xor eax, eax add rsp, 40 ret 5.2.3 GCC + GDB Let’s try this example in GDB. $ gcc -g 2.c -o 2 $ gdb 2 GNU gdb (GDB) 7.6.1-ubuntu Copyright (C) 2013 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Type "show copying" and "show warranty" for details. This GDB was configured as "x86_64-linux-gnu". For bug reporting instructions, please see: 0x0000000000400576 <+73>: mov eax,0x0 0x000000000040057b <+78>: leave 0x000000000040057c <+79>: ret End of assembler dump. 29 5.3. ARM: 3 ARGUMENTS CHAPTER 5. PRINTF() WITH SEVERAL ARGUMENTS Let’s finish printf() execution, execute the instruction zeroing EAX, take a notice that EAX register has exactly zero. RIP now points to the LEAVE instruction, i.e., penultimate in main() function. (gdb) finish Run till exit from #0 __printf (format=0x400628 "a=%d; b=%d; c=%d; d=%d; e=%d; f=%d; g=%d; h=%⤦ Ç d\n") at printf.c:29 a=1; b=2; c=3; d=4; e=5; f=6; g=7; h=8 main () at 2.c:6 6 return 0; Value returned is $1 = 39 (gdb) next 7 }; (gdb) info registers rax 0x0 0 rbx 0x0 0 rcx 0x26 38 rdx 0x7ffff7dd59f0 140737351866864 rsi 0x7fffffd9 2147483609 rdi 0x0 0 rbp 0x7fffffffdf60 0x7fffffffdf60 rsp 0x7fffffffdf40 0x7fffffffdf40 r8 0x7ffff7dd26a0 140737351853728 r9 0x7ffff7a60134 140737348239668 r10 0x7fffffffd5b0 140737488344496 r11 0x7ffff7a95900 140737348458752 r12 0x400440 4195392 r13 0x7fffffffe040 140737488347200 r14 0x0 0 r15 0x0 0 rip 0x40057b 0x40057b ... 5.3 ARM: 3 arguments Traditionally, ARM’s scheme for passing arguments (calling convention) is as follows: the first 4 arguments are passed in the R0-R3 registers; the remaining arguments, via the stack. This resembles the arguments passing scheme in fastcall (44.3) or win64 (44.5.1). 5.3.1 Non-optimizing Keil + ARM mode Listing 5.6: Non-optimizing Keil + ARM mode .text:00000014 printf_main1 .text:00000014 10 40 2D E9 STMFD SP!, {R4,LR} .text:00000018 03 30 A0 E3 MOV R3, #3 .text:0000001C 02 20 A0 E3 MOV R2, #2 .text:00000020 01 10 A0 E3 MOV R1, #1 .text:00000024 1D 0E 8F E2 ADR R0, aADBDCD ; "a=%d; b=%d; c=%d\n" .text:00000028 0D 19 00 EB BL __2printf .text:0000002C 10 80 BD E8 LDMFD SP!, {R4,PC} So, the first 4 arguments are passed via the R0-R3 registers in this order: a pointer to the printf() format string in R0, then 1 in R1, 2 in R2 and 3 in R3. There is nothing unusual so far. 5.3.2 Optimizing Keil + ARM mode Listing 5.7: Optimizing Keil + ARM mode .text:00000014 EXPORT printf_main1 30 5.4. ARM: 8 ARGUMENTS CHAPTER 5. PRINTF() WITH SEVERAL ARGUMENTS .text:00000014 printf_main1 .text:00000014 03 30 A0 E3 MOV R3, #3 .text:00000018 02 20 A0 E3 MOV R2, #2 .text:0000001C 01 10 A0 E3 MOV R1, #1 .text:00000020 1E 0E 8F E2 ADR R0, aADBDCD ; "a=%d; b=%d; c=%d\n" .text:00000024 CB 18 00 EA B __2printf This is optimized (-O3) version for ARM mode and here we see B as the last instruction instead of the familiar BL. Another dierence between this optimized version and the previous one (compiled without optimization) is also in the fact that there is no function prologue and epilogue (instructions that save R0 andLR registers values). The B instruction just jumps to another address, without any manipulation of theLR register, that is, it is analogous to JMP in x86. Why does it work? Because this code is, in fact, eectively equivalent to the previous. There are two main reasons: 1) neither the stack norSP, the stack pointer, is modified; 2) the call to printf() is the last instruction, so there is nothing going on a er it. A er finishing, the printf() function will just return control to the address stored inLR. But the address of the point from where our function was called is now inLR! Consequently, control from printf() will be returned to that point. As a consequence, we do not need to saveLR since we do not need to modifyLR. We do not need to modifyLR since there are no other function calls except printf(). Furthermore, a er this call we do not to do anything! That’s why this optimization is possible. Another similar example was described in “switch()/case/default” section, here (11.1.1). 5.3.3 Optimizing Keil + thumb mode Listing 5.8: Optimizing Keil + thumb mode .text:0000000C printf_main1 .text:0000000C 10 B5 PUSH {R4,LR} .text:0000000E 03 23 MOVS R3, #3 .text:00000010 02 22 MOVS R2, #2 .text:00000012 01 21 MOVS R1, #1 .text:00000014 A4 A0 ADR R0, aADBDCD ; "a=%d; b=%d; c=%d\n" .text:00000016 06 F0 EB F8 BL __2printf .text:0000001A 10 BD POP {R4,PC} There is no significant dierence from the non-optimized code for ARM mode. 5.4 ARM: 8 arguments Let’s use again the example with 9 arguments from the previous section: 5.2. void printf_main2() { printf("a=%d; b=%d; c=%d; d=%d; e=%d; f=%d; g=%d; h=%d\n", 1, 2, 3, 4, 5, 6, 7, 8); }; 5.4.1 Optimizing Keil: ARM mode .text:00000028 printf_main2 .text:00000028 .text:00000028 var_18 = -0x18 .text:00000028 var_14 = -0x14 .text:00000028 var_4 = -4 .text:00000028 .text:00000028 04 E0 2D E5 STR LR, [SP,#var_4]! .text:0000002C 14 D0 4D E2 SUB SP, SP, #0x14 .text:00000030 08 30 A0 E3 MOV R3, #8 .text:00000034 07 20 A0 E3 MOV R2, #7 .text:00000038 06 10 A0 E3 MOV R1, #6 .text:0000003C 05 00 A0 E3 MOV R0, #5 .text:00000040 04 C0 8D E2 ADD R12, SP, #0x18+var_14 .text:00000044 0F 00 8C E8 STMIA R12, {R0-R3} 31 5.4. ARM: 8 ARGUMENTS CHAPTER 5. PRINTF() WITH SEVERAL ARGUMENTS .text:00000048 04 00 A0 E3 MOV R0, #4 .text:0000004C 00 00 8D E5 STR R0, [SP,#0x18+var_18] .text:00000050 03 30 A0 E3 MOV R3, #3 .text:00000054 02 20 A0 E3 MOV R2, #2 .text:00000058 01 10 A0 E3 MOV R1, #1 .text:0000005C 6E 0F 8F E2 ADR R0, aADBDCDDDEDFDGD ; "a=%d; b=%d; c=%d; d=%d; e=%d; f=%d; g⤦ Ç =%"... .text:00000060 BC 18 00 EB BL __2printf .text:00000064 14 D0 8D E2 ADD SP, SP, #0x14 .text:00000068 04 F0 9D E4 LDR PC, [SP+4+var_4],#4 This code can be divided into several parts: • Function prologue: The very first “STR LR, [SP,#var_4]!” instruction savesLR on the stack, because we will use this register for the printf() call. The second “SUB SP, SP, #0x14” instruction decreasesSP, the stack pointer, in order to allocate 0x14 (20) bytes on the stack. Indeed, we need to pass 5 32-bit values via the stack to the printf() function, and each one occupies 4 bytes, that is 5 ∗ 4 = 20 —exactly. The other 4 32-bit values will be passed in registers. • Passing 5, 6, 7 and 8 via stack: Then, the values 5, 6, 7 and 8 are written to the R0, R1, R2 and R3 registers respectively. Then, the “ADD R12, SP, #0x18+var_14” instruction writes an address of the point in the stack, where these 4 variables will be written, into the R12 register. var_14 is an assembly macro, equal to −0푥14, such macros are created by IDA to succinctly denote code accessing the stack. var_? macros created by IDA reflecting local variables in the stack. So, 푆푃 + 4 will be written into the R12 register. The next “STMIA R12, R0-R3” instruction writes R0-R3 registers contents at the point in memory to which R12 pointing. STMIA instruction meaning Store Multiple Increment A er. Increment A er means that R12 will be increased by 4 a er each register value is written. • Passing 4 via stack: 4 is stored in R0 and then, this value, with the help of “STR R0, [SP,#0x18+var_18]” instruction, is saved on the stack. var_18 is −0푥18, oset will be 0, so, the value from the R0 register (4) will be written to the point whereSP is pointing to. • Passing 1, 2 and 3 via registers: Values of the first 3 numbers (a, b, c) (1, 2, 3 respectively) are passed in the R1, R2 and R3 registers right before the printf() call, and the other 5 values are passed via the stack: • printf() call: • Function epilogue: The “ADD SP, SP, #0x14” instruction returns theSP pointer back to its former point, thus cleaning the stack. Of course, what was written on the stack will stay there, but it all will be rewritten during the execution of subsequent functions. The “LDR PC, [SP+4+var_4],#4” instruction loads the savedLR value from the stack into thePC register, thus caus- ing the function to exit. 5.4.2 Optimizing Keil: thumb mode .text:0000001C printf_main2 .text:0000001C .text:0000001C var_18 = -0x18 .text:0000001C var_14 = -0x14 .text:0000001C var_8 = -8 .text:0000001C .text:0000001C 00 B5 PUSH {LR} .text:0000001E 08 23 MOVS R3, #8 .text:00000020 85 B0 SUB SP, SP, #0x14 .text:00000022 04 93 STR R3, [SP,#0x18+var_8] .text:00000024 07 22 MOVS R2, #7 .text:00000026 06 21 MOVS R1, #6 .text:00000028 05 20 MOVS R0, #5 32 5.4. ARM: 8 ARGUMENTS CHAPTER 5. PRINTF() WITH SEVERAL ARGUMENTS .text:0000002A 01 AB ADD R3, SP, #0x18+var_14 .text:0000002C 07 C3 STMIA R3!, {R0-R2} .text:0000002E 04 20 MOVS R0, #4 .text:00000030 00 90 STR R0, [SP,#0x18+var_18] .text:00000032 03 23 MOVS R3, #3 .text:00000034 02 22 MOVS R2, #2 .text:00000036 01 21 MOVS R1, #1 .text:00000038 A0 A0 ADR R0, aADBDCDDDEDFDGD ; "a=%d; b=%d; c=%d; d=%d; e=%d; f=%d; ⤦ Ç g=%"... .text:0000003A 06 F0 D9 F8 BL __2printf .text:0000003E .text:0000003E loc_3E ; CODE XREF: example13_f+16 .text:0000003E 05 B0 ADD SP, SP, #0x14 .text:00000040 00 BD POP {PC} Almost same as in previous example, however, this is thumb code and values are packed into stack dierently: 8 for the first time, then 5, 6, 7 for the second and 4 for the third. 5.4.3 Optimizing Xcode (LLVM): ARM mode __text:0000290C _printf_main2 __text:0000290C __text:0000290C var_1C = -0x1C __text:0000290C var_C = -0xC __text:0000290C __text:0000290C 80 40 2D E9 STMFD SP!, {R7,LR} __text:00002910 0D 70 A0 E1 MOV R7, SP __text:00002914 14 D0 4D E2 SUB SP, SP, #0x14 __text:00002918 70 05 01 E3 MOV R0, #0x1570 __text:0000291C 07 C0 A0 E3 MOV R12, #7 __text:00002920 00 00 40 E3 MOVT R0, #0 __text:00002924 04 20 A0 E3 MOV R2, #4 __text:00002928 00 00 8F E0 ADD R0, PC, R0 __text:0000292C 06 30 A0 E3 MOV R3, #6 __text:00002930 05 10 A0 E3 MOV R1, #5 __text:00002934 00 20 8D E5 STR R2, [SP,#0x1C+var_1C] __text:00002938 0A 10 8D E9 STMFA SP, {R1,R3,R12} __text:0000293C 08 90 A0 E3 MOV R9, #8 __text:00002940 01 10 A0 E3 MOV R1, #1 __text:00002944 02 20 A0 E3 MOV R2, #2 __text:00002948 03 30 A0 E3 MOV R3, #3 __text:0000294C 10 90 8D E5 STR R9, [SP,#0x1C+var_C] __text:00002950 A4 05 00 EB BL _printf __text:00002954 07 D0 A0 E1 MOV SP, R7 __text:00002958 80 80 BD E8 LDMFD SP!, {R7,PC} Almost the same what we already figured out, with the exception of STMFA (Store Multiple Full Ascending) instruction, it is synonym to STMIB (Store Multiple Increment Before) instruction. This instruction increasing value in theSP register and only then writing next register value into memory, but not vice versa. Another thing we easily spot is the instructions are ostensibly located randomly. For instance, value in the R0 register is prepared in three places, at addresses 0x2918, 0x2920 and 0x2928, when it would be possible to do it in one single point. However, optimizing compiler has its own reasons about how to place instructions better. Usually, processor attempts to simultaneously execute instructions located side-by-side. For example, instructions like “MOVT R0, #0” and “ADD R0, PC, R0” cannot be executed simultaneously since they both modifying the R0 register. On the other hand, “MOVT R0, #0” and “MOV R2, #4” instructions can be executed simultaneously since eects of their execution are not conflicting with each other. Presumably, compiler tries to generate code in such a way, where it is possible, of course. 5.4.4 Optimizing Xcode (LLVM): thumb-2 mode __text:00002BA0 _printf_main2 33 5.5. BY THE WAY CHAPTER 5. PRINTF() WITH SEVERAL ARGUMENTS __text:00002BA0 __text:00002BA0 var_1C = -0x1C __text:00002BA0 var_18 = -0x18 __text:00002BA0 var_C = -0xC __text:00002BA0 __text:00002BA0 80 B5 PUSH {R7,LR} __text:00002BA2 6F 46 MOV R7, SP __text:00002BA4 85 B0 SUB SP, SP, #0x14 __text:00002BA6 41 F2 D8 20 MOVW R0, #0x12D8 __text:00002BAA 4F F0 07 0C MOV.W R12, #7 __text:00002BAE C0 F2 00 00 MOVT.W R0, #0 __text:00002BB2 04 22 MOVS R2, #4 __text:00002BB4 78 44 ADD R0, PC ; char * __text:00002BB6 06 23 MOVS R3, #6 __text:00002BB8 05 21 MOVS R1, #5 __text:00002BBA 0D F1 04 0E ADD.W LR, SP, #0x1C+var_18 __text:00002BBE 00 92 STR R2, [SP,#0x1C+var_1C] __text:00002BC0 4F F0 08 09 MOV.W R9, #8 __text:00002BC4 8E E8 0A 10 STMIA.W LR, {R1,R3,R12} __text:00002BC8 01 21 MOVS R1, #1 __text:00002BCA 02 22 MOVS R2, #2 __text:00002BCC 03 23 MOVS R3, #3 __text:00002BCE CD F8 10 90 STR.W R9, [SP,#0x1C+var_C] __text:00002BD2 01 F0 0A EA BLX _printf __text:00002BD6 05 B0 ADD SP, SP, #0x14 __text:00002BD8 80 BD POP {R7,PC} Almost the same as in previous example, with the exception the thumb-instructions are used here instead. 5.5 By the way By the way, this dierence between passing arguments in x86, x64, fastcall and ARM is a good illustration the CPU is not aware of how arguments is passed to functions. It is also possible to create hypothetical compiler which is able to pass arguments via a special structure not using stack at all. 34 CHAPTER 6. SCANF() Chapter 6 scanf() Now let’s use scanf(). #include int main() { int x; printf ("Enter X:\n"); scanf ("%d", &x); printf ("You entered %d...\n", x); return 0; }; OK, I agree, it is not clever to use scanf() today. But I wanted to illustrate passing pointer to int. 6.1 About pointers It is one of the most fundamental things in computer science. O en, large array, structure or object, it is too costly to pass to other function, while passing its address is much easier. More than that: if calling function must modify something in the large array or structure, to return it as a whole is absurdly as well. So the simplest thing to do is to pass an address of array or structure to function, and let it change what must be changed. In C/C++ it is just an address of some point in memory. In x86, address is represented as 32-bit number (i.e., occupying 4 bytes), while in x86–64 it is 64-bit number (occupying 8 bytes). By the way, that is the reason of some people’s indignation related to switching to x86-64 —all pointers on x64- architecture will require twice as more space. With some eort, it is possible to work only with untyped pointers; e.g. standard C function memcpy(), copying a block from one place in memory to another, takes 2 pointers of void* type on input, since it is impossible to predict block type you would like to copy. And it is not even important to know, only block size is important. Also pointers are widely used when function needs to return more than one value (we will back to this in future (9)). scanf() is just that case. In addition to the function’s need to show how many values were read successfully, it also should return all these values. In C/C++ pointer type is needed only for type checking on compiling stage. Internally, in compiled code, there is no infor- mation about pointers types. 6.2 x86 6.2.1 MSVC What we got a er compiling in MSVC 2010: CONST SEGMENT $SG3831 DB ’Enter X:’, 0aH, 00H $SG3832 DB ’%d’, 00H 35 6.2. X86 CHAPTER 6. SCANF() $SG3833 DB ’You entered %d...’, 0aH, 00H CONST ENDS PUBLIC _main EXTRN _scanf:PROC EXTRN _printf:PROC ; Function compile flags: /Odtp _TEXT SEGMENT _x$ = -4 ; size = 4 _main PROC push ebp mov ebp, esp push ecx push OFFSET $SG3831 ; ’Enter X:’ call _printf add esp, 4 lea eax, DWORD PTR _x$[ebp] push eax push OFFSET $SG3832 ; ’%d’ call _scanf add esp, 8 mov ecx, DWORD PTR _x$[ebp] push ecx push OFFSET $SG3833 ; ’You entered %d...’ call _printf add esp, 8 ; return 0 xor eax, eax mov esp, ebp pop ebp ret 0 _main ENDP _TEXT ENDS Variable x is local. C/C++ standard tell us it must be visible only in this function and not from any other point. Traditionally, local variables are placed in the stack. Probably, there could be other ways, but in x86 it is so. Next instruction a er function prologue, PUSH ECX, has not a goal to save ECX state (notice absence of corresponding POP ECX at the function end). In fact, this instruction just allocates 4 bytes on the stack for x variable storage. x will be accessed with the assistance of the _x$ macro (it equals to -4) and the EBP register pointing to current frame. Over a span of function execution, EBP is pointing to current stack frame and it is possible to have an access to local variables and function arguments via EBP+offset. It is also possible to use ESP, but it is o en changing and not very convenient. So it can be said, the value of the EBP is frozen state of the value of the ESP at the moment of function execution start. A very typical stack frame layout in 32-bit environment is: ...... EBP-8 local variable #2, marked in IDA as var_8 EBP-4 local variable #1, marked in IDA as var_4 EBP saved value of EBP EBP+4 return address EBP+8 argument#1, marked in IDA as arg_0 EBP+0xC argument#2, marked in IDA as arg_4 EBP+0x10 argument#3, marked in IDA as arg_8 ...... Function scanf() in our example has two arguments. First is pointer to the string containing “%d” and second —address of variable x. First of all, address of the x variable is placed into the EAX register by lea eax, DWORD PTR _x$[ebp] instruction LEA meaning load eective address but over a time it changed its primary application (B.6.2). 36 6.2. X86 CHAPTER 6. SCANF() It can be said, LEA here just stores sum of the value in the EBP register and _x$ macro to the EAX register. It is the same as lea eax, [ebp-4]. So, 4 subtracting from value in the EBP register and result is placed to the EAX register. And then value in the EAX register is pushing into stack and scanf() is called. A er that, printf() is called. First argument is pointer to string: “You entered %d...\n”. Second argument is prepared as: mov ecx, [ebp-4], this instruction places to the ECX not address of the x variable, but its contents. A er, value in the ECX is placed on the stack and the last printf() called. 6.2.2 MSVC + OllyDbg Let’s try this example in OllyDbg. Let’s load, press F8 (step over) until we get into our executable file instead of ntdll.dll. Scroll up until main() appears. Let’s click on the first instruction (PUSH EBP), press F2, then F9 (Run) and breakpoint triggers on the main() begin. Let’s trace to the place where the address of 푥 variable is prepared: fig. 6.2. It is possible to right-click on EAX in registers window and then “Follow in stack”. This address will appear in stack window. Look, this is a variable in the local stack. I drawed a red arrow there. And there are some garbage (0x77D478). Now address of the stack element, with the help of PUSH, will be written to the same stack, nearly. Let’s trace by F8 until scanf() execution finished. During the moment of scanf() execution, we enter, for example, 123, in the console window: Figure 6.1: Console output scanf() executed here: fig. 6.3. scanf() returns 1 in EAX, which means, it have read one value successfully. The element of stack of our attention now contain 0x7B (123). Further, this value is copied from the stack to the ECX register and passed into printf(): fig. 6.4. Figure 6.2: OllyDbg: address of the local variable is computed 37 6.2. X86 CHAPTER 6. SCANF() Figure 6.3: OllyDbg: scanf() executed Figure 6.4: OllyDbg: preparing the value for passing into printf() 6.2.3 GCC Let’s try to compile this code in GCC 4.4.1 under Linux: main proc near var_20 = dword ptr -20h var_1C = dword ptr -1Ch var_4 = dword ptr -4 push ebp mov ebp, esp and esp, 0FFFFFFF0h sub esp, 20h mov [esp+20h+var_20], offset aEnterX ; "Enter X:" call _puts mov eax, offset aD ; "%d" lea edx, [esp+20h+var_4] mov [esp+20h+var_1C], edx mov [esp+20h+var_20], eax 38 6.3. X64 CHAPTER 6. SCANF() call ___isoc99_scanf mov edx, [esp+20h+var_4] mov eax, offset aYouEnteredD___ ; "You entered %d...\n" mov [esp+20h+var_1C], edx mov [esp+20h+var_20], eax call _printf mov eax, 0 leave retn main endp GCC replaced first the printf() call to the puts(), it was already described (2.3.3) why it was done. As before —arguments are placed on the stack by MOV instruction. 6.3 x64 All the same, but registers are used instead of stack for arguments passing. 6.3.1 MSVC Listing 6.1: MSVC 2012 x64 _DATA SEGMENT $SG1289 DB ’Enter X:’, 0aH, 00H $SG1291 DB ’%d’, 00H $SG1292 DB ’You entered %d...’, 0aH, 00H _DATA ENDS _TEXT SEGMENT x$ = 32 main PROC $LN3: sub rsp, 56 lea rcx, OFFSET FLAT:$SG1289 ; ’Enter X:’ call printf lea rdx, QWORD PTR x$[rsp] lea rcx, OFFSET FLAT:$SG1291 ; ’%d’ call scanf mov edx, DWORD PTR x$[rsp] lea rcx, OFFSET FLAT:$SG1292 ; ’You entered %d...’ call printf ; return 0 xor eax, eax add rsp, 56 ret 0 main ENDP _TEXT ENDS 6.3.2 GCC Listing 6.2: GCC 4.4.6 -O3 x64 .LC0: .string "Enter X:" .LC1: .string "%d" .LC2: .string "You entered %d...\n" 39 6.4. ARM CHAPTER 6. SCANF() main: sub rsp, 24 mov edi, OFFSET FLAT:.LC0 ; "Enter X:" call puts lea rsi, [rsp+12] mov edi, OFFSET FLAT:.LC1 ; "%d" xor eax, eax call __isoc99_scanf mov esi, DWORD PTR [rsp+12] mov edi, OFFSET FLAT:.LC2 ; "You entered %d...\n" xor eax, eax call printf ; return 0 xor eax, eax add rsp, 24 ret 6.4 ARM 6.4.1 Optimizing Keil + thumb mode .text:00000042 scanf_main .text:00000042 .text:00000042 var_8 = -8 .text:00000042 .text:00000042 08 B5 PUSH {R3,LR} .text:00000044 A9 A0 ADR R0, aEnterX ; "Enter X:\n" .text:00000046 06 F0 D3 F8 BL __2printf .text:0000004A 69 46 MOV R1, SP .text:0000004C AA A0 ADR R0, aD ; "%d" .text:0000004E 06 F0 CD F8 BL __0scanf .text:00000052 00 99 LDR R1, [SP,#8+var_8] .text:00000054 A9 A0 ADR R0, aYouEnteredD___ ; "You entered %d...\n" .text:00000056 06 F0 CB F8 BL __2printf .text:0000005A 00 20 MOVS R0, #0 .text:0000005C 08 BD POP {R3,PC} A pointer to a int-typed variable must be passed to a scanf() so it can return value via it. int is 32-bit value, so we need 4 bytes for storing it somewhere in memory, and it fits exactly in 32-bit register. A place for the local variable x is allocated in the stack and IDA named it var_8, however, it is not necessary to allocate it sinceSP stack pointer is already pointing to the space may be used instantly. So,SP stack pointer value is copied to the R1 register and, together with format-string, passed into scanf(). Later, with the help of the LDR instruction, this value is moved from stack into the R1 register in order to be passed into printf(). Examples compiled for ARM-mode and also examples compiled with Xcode LLVM are not dier significantly from what we saw here, so they are omitted. 6.5 Global variables What if x variable from previous example will not be local but global variable? Then it will be accessible from any point, not only from function body. Global variables are considered as anti-pattern, but for the sake of experiment we could do this. #include int x; int main() { 40 6.5. GLOBAL VARIABLES CHAPTER 6. SCANF() printf ("Enter X:\n"); scanf ("%d", &x); printf ("You entered %d...\n", x); return 0; }; 6.5.1 MSVC: x86 _DATA SEGMENT COMM _x:DWORD $SG2456 DB ’Enter X:’, 0aH, 00H $SG2457 DB ’%d’, 00H $SG2458 DB ’You entered %d...’, 0aH, 00H _DATA ENDS PUBLIC _main EXTRN _scanf:PROC EXTRN _printf:PROC ; Function compile flags: /Odtp _TEXT SEGMENT _main PROC push ebp mov ebp, esp push OFFSET $SG2456 call _printf add esp, 4 push OFFSET _x push OFFSET $SG2457 call _scanf add esp, 8 mov eax, DWORD PTR _x push eax push OFFSET $SG2458 call _printf add esp, 8 xor eax, eax pop ebp ret 0 _main ENDP _TEXT ENDS Now x variable is defined in the _DATA segment. Memory in local stack is not allocated anymore. All accesses to it are not via stack but directly to process memory. Not initialized global variables takes no place in the executable file (indeed, why we should allocate a place in the executable file for initially zeroed variables?), but when someone will access this place in memory,OS will allocate a block of zeroes there 1. Now let’s assign value to variable explicitly: int x=10; // default value We got: _DATA SEGMENT _x DD 0aH ... Here we see value 0xA of DWORD type (DD meaning DWORD = 32 bit). 1That is howVM behaves 41 6.5. GLOBAL VARIABLES CHAPTER 6. SCANF() If you will open compiled .exe in IDA, you will see the x variable placed at the beginning of the _DATA segment, and a er you’ll see text strings. If you will open compiled .exe in IDA from previous example where x value is not defined, you’ll see something like this: .data:0040FA80 _x dd ? ; DATA XREF: _main+10 .data:0040FA80 ; _main+22 .data:0040FA84 dword_40FA84 dd ? ; DATA XREF: _memset+1E .data:0040FA84 ; unknown_libname_1+28 .data:0040FA88 dword_40FA88 dd ? ; DATA XREF: ___sbh_find_block+5 .data:0040FA88 ; ___sbh_free_block+2BC .data:0040FA8C ; LPVOID lpMem .data:0040FA8C lpMem dd ? ; DATA XREF: ___sbh_find_block+B .data:0040FA8C ; ___sbh_free_block+2CA .data:0040FA90 dword_40FA90 dd ? ; DATA XREF: _V6_HeapAlloc+13 .data:0040FA90 ; __calloc_impl+72 .data:0040FA94 dword_40FA94 dd ? ; DATA XREF: ___sbh_free_block+2FE _xmarked as? among other variables not required to be initialized. This means that a er loading .exe to memory, a space for all these variables will be allocated and a random garbage will be here. But in an .exe file these not initialized variables are not occupy anything. E.g. it is suitable for large arrays. 6.5.2 MSVC: x86 + OllyDbg Things are even simpler here: fig. 6.5. Variable is located in the data segment. By the way, a er PUSH instruction, pushing 푥 address, is executed, the address will appear in stack, and it is possible to right-click on that element and select “Follow in dump”. And the variable will appear in the memory window at le . A er we enter 123 in the console, 0x7B will appear here. But why the very first byte is 7B? Thinking logically, a 00 00 00 7B should be there. This is what called endianness, and little-endian is used in x86. This mean that lowest byte is written first, and highest written last. More about it: 33. Some time a er, 32-bit value from this place of memory is loaded into EAX and passed into printf(). 푥 variable address in the memory is 0xDC3390. In OllyDbg we can see process memory map (Alt-M) and we will see that this address is inside of .data PE-segment of our program: fig. 6.6. Figure 6.5: OllyDbg: a er scanf() execution 42 6.5. GLOBAL VARIABLES CHAPTER 6. SCANF() Figure 6.6: OllyDbg: process memory map 6.5.3 GCC: x86 It is almost the same in Linux, except segment names and properties: not initialized variables are located in the_bsssegment. In ELF file format this segment has such attributes: ; Segment type: Uninitialized ; Segment permissions: Read/Write If to statically assign a value to variable, e.g. 10, it will be placed in the _data segment, this is segment with the following attributes: ; Segment type: Pure data ; Segment permissions: Read/Write 6.5.4 MSVC: x64 Listing 6.3: MSVC 2012 x64 _DATA SEGMENT COMM x:DWORD $SG2924 DB ’Enter X:’, 0aH, 00H $SG2925 DB ’%d’, 00H $SG2926 DB ’You entered %d...’, 0aH, 00H _DATA ENDS _TEXT SEGMENT main PROC $LN3: sub rsp, 40 lea rcx, OFFSET FLAT:$SG2924 ; ’Enter X:’ call printf lea rdx, OFFSET FLAT:x lea rcx, OFFSET FLAT:$SG2925 ; ’%d’ call scanf mov edx, DWORD PTR x 43 6.5. GLOBAL VARIABLES CHAPTER 6. SCANF() lea rcx, OFFSET FLAT:$SG2926 ; ’You entered %d...’ call printf ; return 0 xor eax, eax add rsp, 40 ret 0 main ENDP _TEXT ENDS Almost the same code as in x86. Take a notice that 푥 variable address is passed to scanf() using LEA instruction, while the value of variable is passed to the second printf() using MOV instruction. “DWORD PTR”—is a part of assembly language (no related to machine codes), showing that the variable data type is 32-bit and the MOV instruction should be encoded ac- cordingly. 6.5.5 ARM: Optimizing Keil + thumb mode .text:00000000 ; Segment type: Pure code .text:00000000 AREA .text, CODE ... .text:00000000 main .text:00000000 PUSH {R4,LR} .text:00000002 ADR R0, aEnterX ; "Enter X:\n" .text:00000004 BL __2printf .text:00000008 LDR R1, =x .text:0000000A ADR R0, aD ; "%d" .text:0000000C BL __0scanf .text:00000010 LDR R0, =x .text:00000012 LDR R1, [R0] .text:00000014 ADR R0, aYouEnteredD___ ; "You entered %d...\n" .text:00000016 BL __2printf .text:0000001A MOVS R0, #0 .text:0000001C POP {R4,PC} ... .text:00000020 aEnterX DCB "Enter X:",0xA,0 ; DATA XREF: main+2 .text:0000002A DCB 0 .text:0000002B DCB 0 .text:0000002C off_2C DCD x ; DATA XREF: main+8 .text:0000002C ; main+10 .text:00000030 aD DCB "%d",0 ; DATA XREF: main+A .text:00000033 DCB 0 .text:00000034 aYouEnteredD___ DCB "You entered %d...",0xA,0 ; DATA XREF: main+14 .text:00000047 DCB 0 .text:00000047 ; .text ends .text:00000047 ... .data:00000048 ; Segment type: Pure data .data:00000048 AREA .data, DATA .data:00000048 ; ORG 0x48 .data:00000048 EXPORT x .data:00000048 x DCD 0xA ; DATA XREF: main+8 .data:00000048 ; main+10 .data:00000048 ; .data ends So, x variable is now global and somehow, it is now located in another segment, namely data segment (.data). One could ask, why text strings are located in code segment (.text) and x can be located right here? Since this is variable, and by its definition, it can be changed. And probably, can be changed very o en. Segment of code not infrequently can be located in microcontroller ROM (remember, we now deal with embedded microelectronics, and memory scarcity is common here), and changeable variables —in RAM2. It is not very economically to store constant variables in RAM when one have ROM. 2Random-access memory 44 6.6. SCANF() RESULT CHECKING CHAPTER 6. SCANF() Furthermore, data segment with constants in RAM must be initialized before, since a er RAM turning on, obviously, it contain random information. Onwards, we see, in code segment, a pointer to the x (off_2C) variable, and all operations with variable occurred via this pointer. This is because x variable can be located somewhere far from this code fragment, so its address must be saved somewhere in close proximity to the code. LDR instruction in thumb mode can address only variable in range of 1020 bytes from the point it is located. Same instruction in ARM-mode —variables in range ±4095 bytes, this, address of the x variable must be located somewhere in close proximity, because, there is no guarantee the linker will able to place this variable near the code, it could be even in external memory chip! One more thing: if variable will be declared as const, Keil compiler shall allocate it in the .constdata segment. Perhaps, therea er, linker will able to place this segment in ROM too, along with code segment. 6.6 scanf() result checking As I noticed before, it is slightly old-fashioned to use scanf() today. But if we have to, we need at least check if scanf() finished correctly without error. #include int main() { int x; printf ("Enter X:\n"); if (scanf ("%d", &x)==1) printf ("You entered %d...\n", x); else printf ("What you entered? Huh?\n"); return 0; }; By standard, scanf()3 function returns number of fields it successfully read. In our case, if everything went fine and user entered a number, scanf() will return 1 or 0 or EOF in case of error. I added C code for scanf() result checking and printing error message in case of error. This works predictably: C:\...>ex3.exe Enter X: 123 You entered 123... C:\...>ex3.exe Enter X: ouch What you entered? Huh? 6.6.1 MSVC: x86 What we got in assembly language (MSVC 2010): lea eax, DWORD PTR _x$[ebp] push eax push OFFSET $SG3833 ; ’%d’, 00H call _scanf add esp, 8 cmp eax, 1 jne SHORT $LN2@main mov ecx, DWORD PTR _x$[ebp] push ecx 3MSDN: scanf, wscanf: http://msdn.microsoft.com/en-us/library/9y6s16x1(VS.71).aspx 45 6.6. SCANF() RESULT CHECKING CHAPTER 6. SCANF() push OFFSET $SG3834 ; ’You entered %d...’, 0aH, 00H call _printf add esp, 8 jmp SHORT $LN1@main $LN2@main: push OFFSET $SG3836 ; ’What you entered? Huh?’, 0aH, 00H call _printf add esp, 4 $LN1@main: xor eax, eax Caller function (main()) must have access to the result of callee function (scanf()), so callee leaves this value in the EAX register. A er, we check it with the help of instruction CMP EAX, 1 (CoMPare), in other words, we compare value in the EAX register with 1. JNE conditional jump follows CMP instruction. JNE means Jump if Not Equal. So, if value in the EAX register not equals to 1, then the processor will pass execution to the address mentioned in operand of JNE, in our case it is $LN2@main. Passing control to this address, CPU will execute function printf() with argument “What you entered? Huh?”. But if everything is fine, conditional jump will not be taken, and another printf() call will be executed, with two arguments: ’You entered %d...’ and value of variable x. Since second subsequentprintf()not needed to be executed, there isJMPa er (unconditional jump), it will pass control to the point a er second printf() and before XOR EAX, EAX instruction, which implement return 0. So, it can be said that comparing a value with another is usually implemented by CMP/Jcc instructions pair, where cc is condition code. CMP comparing two values and set processor flags4. Jcc check flags needed to be checked and pass control to mentioned address (or not pass). But in fact, this could be perceived paradoxical, but CMP instruction is in fact SUB (subtract). All arithmetic instructions set processor flags too, not only CMP. If we compare 1 and 1, 1 − 1 will be 0 in result, ZF flag will be set (meaning the last result was 0). There is no any other circumstances when it is possible except when operands are equal. JNE checks only ZF flag and jumping only if it is not set. JNE is in fact a synonym of JNZ (Jump if Not Zero) instruction. Assembler translating both JNE and JNZ instructions into one single opcode. So, CMP instruction can be replaced to SUB instruction and almost everything will be fine, but the dierence is in the SUB alter the value of the first operand. CMP is “SUB without saving result”. 6.6.2 MSVC: x86: IDA It’s time to run IDA and try to do something in it. By the way, it is good idea to use /MD option in MSVC for beginners: this mean that all these standard functions will not be linked with executable file, but will be imported from the MSVCR*.DLL file instead. Thus it will be easier to see which standard function used and where. While analysing code in IDA, it is very advisable to do notes for oneself (and others). For example, analysing this example, we see that JNZ will be triggered in case of error. So it’s possible to move cursor to the label, press “n” and rename it to “error”. Another label—into “exit”. What I’ve got: .text:00401000 _main proc near .text:00401000 .text:00401000 var_4 = dword ptr -4 .text:00401000 argc = dword ptr 8 .text:00401000 argv = dword ptr 0Ch .text:00401000 envp = dword ptr 10h .text:00401000 .text:00401000 push ebp .text:00401001 mov ebp, esp .text:00401003 push ecx .text:00401004 push offset Format ; "Enter X:\n" .text:00401009 call ds:printf .text:0040100F add esp, 4 .text:00401012 lea eax, [ebp+var_4] .text:00401015 push eax .text:00401016 push offset aD ; "%d" .text:0040101B call ds:scanf .text:00401021 add esp, 8 .text:00401024 cmp eax, 1 4About x86 flags, see also: http://en.wikipedia.org/wiki/FLAGS_register_(computing). 46 6.6. SCANF() RESULT CHECKING CHAPTER 6. SCANF() .text:00401027 jnz short error .text:00401029 mov ecx, [ebp+var_4] .text:0040102C push ecx .text:0040102D push offset aYou ; "You entered %d...\n" .text:00401032 call ds:printf .text:00401038 add esp, 8 .text:0040103B jmp short exit .text:0040103D .text:0040103D error: ; CODE XREF: _main+27 .text:0040103D push offset aWhat ; "What you entered? Huh?\n" .text:00401042 call ds:printf .text:00401048 add esp, 4 .text:0040104B .text:0040104B exit: ; CODE XREF: _main+3B .text:0040104B xor eax, eax .text:0040104D mov esp, ebp .text:0040104F pop ebp .text:00401050 retn .text:00401050 _main endp Now it’s slightly easier to understand the code. However, it’s not good idea to comment every instruction excessively. A part of function can also be hidden in IDA: a block should be marked, then “-” on numerical pad is pressed and text to be entered. I’ve hide two parts and gave names to them: .text:00401000 _text segment para public ’CODE’ use32 .text:00401000 assume cs:_text .text:00401000 ;org 401000h .text:00401000 ; ask for X .text:00401012 ; get X .text:00401024 cmp eax, 1 .text:00401027 jnz short error .text:00401029 ; print result .text:0040103B jmp short exit .text:0040103D .text:0040103D error: ; CODE XREF: _main+27 .text:0040103D push offset aWhat ; "What you entered? Huh?\n" .text:00401042 call ds:printf .text:00401048 add esp, 4 .text:0040104B .text:0040104B exit: ; CODE XREF: _main+3B .text:0040104B xor eax, eax .text:0040104D mov esp, ebp .text:0040104F pop ebp .text:00401050 retn .text:00401050 _main endp To unhide these parts, “+” on numerical pad can be used. By pressing “space”, we can see how IDA can represent a function as a graph: fig. 6.7. There are two arrows a er each conditional jump: green and red. Green arrow pointing to the block which will be executed if jump is triggered, and red if otherwise. It is possible to fold nodes is this mode and give them names as well (“group nodes”). I did it for 3 blocks: fig. 6.8. It’s very useful. It can be said, a very important part of reverse engineer’s job is to reduce information he/she have. 47 6.6. SCANF() RESULT CHECKING CHAPTER 6. SCANF() Figure 6.7: Graph mode in IDA 48 6.6. SCANF() RESULT CHECKING CHAPTER 6. SCANF() Figure 6.8: Graph mode in IDA with 3 nodes folded 6.6.3 MSVC: x86 + OllyDbg Let’s try to hack our program in OllyDbg, forcing it to think scanf() working always without error. When address of local variable is passed intoscanf(), initially this variable contain some random garbage, that is0x4CD478 in case: fig. 6.10. When scanf() is executing, I enter in the console something definitely not a number, like “asdasd”. scanf() finishing with 0 in EAX, which mean, an error occurred: fig. 6.11. We can also see to the local variable in the stack and notice that it’s not changed. Indeed, what scanf() would write there? It just did nothing except returning zero. Now let’s try to “hack” our program. Let’s right-click on EAX, there will also be “Set to 1” among other options. This is what we need. 1 now in EAX, so the following check will executed as we need, and printf() will print value of variable in the stack. Let’s run (F9) and we will see this in console window: Figure 6.9: console window Indeed, 5035128 is a decimal representation of the number in stack (0x4CD478)! 49 6.6. SCANF() RESULT CHECKING CHAPTER 6. SCANF() Figure 6.10: OllyDbg: passing variable address into scanf() Figure 6.11: OllyDbg: scanf() returning error 6.6.4 MSVC: x86 + Hiew This can be also a simple example of executable file patching. We may try to patch executable, so the program will always print numbers, no matter what we entered. Assuming the executable compiled against external MSVCR*.DLL (i.e., with /MD option)5, we may find main() function at the very beginning of .text section. Let’s open executable in Hiew, find the very beginning of .text section (Enter, F8, F6, Enter, Enter). We will see this: fig. 6.12. Hiew finds ASCIIZ6 strings and displays them, as well as imported function names. Move cursor to the address .00401027 (with the JNZ instruction we should bypass), press F3, and then type “9090” (meaning two NOP7-s): fig. 6.13. Then F9 (update). Now the executable saved to disk. It will behave as we wanted. Two NOP-s are probably not quite æsthetically as it could be. Other way to patch this instruction is to write just 0 to the second opcode byte (jump oset), so that JNZ will always jump to the next instruction. 5that’s what also called “dynamic linking” 6ASCII Zero (null-terminated ASCII string) 7No OPeration 50 6.6. SCANF() RESULT CHECKING CHAPTER 6. SCANF() We can do the opposite: replace first byte to EB while not touching the second byte (jump oset). We’ll got here always triggered unconditional jump. The error message will be printed always, no matter what number was entered. Figure 6.12: Hiew: main() function 51 6.6. SCANF() RESULT CHECKING CHAPTER 6. SCANF() Figure 6.13: Hiew: replacing JNZ by two NOP-s 6.6.5 GCC: x86 Code generated by GCC 4.4.1 in Linux is almost the same, except dierences we already considered. 6.6.6 MSVC: x64 Since we work here with int-typed variables, which are still 32-bit in x86-64, we see how 32-bit part of registers (prefixed with E-) are used here as well. While working with pointers, however, 64-bit register parts are used, prefied with R-. Listing 6.4: MSVC 2012 x64 _DATA SEGMENT $SG2924 DB ’Enter X:’, 0aH, 00H $SG2926 DB ’%d’, 00H $SG2927 DB ’You entered %d...’, 0aH, 00H $SG2929 DB ’What you entered? Huh?’, 0aH, 00H _DATA ENDS _TEXT SEGMENT x$ = 32 main PROC $LN5: sub rsp, 56 lea rcx, OFFSET FLAT:$SG2924 ; ’Enter X:’ call printf lea rdx, QWORD PTR x$[rsp] lea rcx, OFFSET FLAT:$SG2926 ; ’%d’ call scanf 52 6.6. SCANF() RESULT CHECKING CHAPTER 6. SCANF() cmp eax, 1 jne SHORT $LN2@main mov edx, DWORD PTR x$[rsp] lea rcx, OFFSET FLAT:$SG2927 ; ’You entered %d...’ call printf jmp SHORT $LN1@main $LN2@main: lea rcx, OFFSET FLAT:$SG2929 ; ’What you entered? Huh?’ call printf $LN1@main: ; return 0 xor eax, eax add rsp, 56 ret 0 main ENDP _TEXT ENDS END 6.6.7 ARM: Optimizing Keil + thumb mode Listing 6.5: Optimizing Keil + thumb mode var_8 = -8 PUSH {R3,LR} ADR R0, aEnterX ; "Enter X:\n" BL __2printf MOV R1, SP ADR R0, aD ; "%d" BL __0scanf CMP R0, #1 BEQ loc_1E ADR R0, aWhatYouEntered ; "What you entered? Huh?\n" BL __2printf loc_1A ; CODE XREF: main+26 MOVS R0, #0 POP {R3,PC} loc_1E ; CODE XREF: main+12 LDR R1, [SP,#8+var_8] ADR R0, aYouEnteredD___ ; "You entered %d...\n" BL __2printf B loc_1A New instructions here are CMP and BEQ8. CMP is akin to the x86 instruction bearing the same name, it subtracts one argument from another and saves flags. BEQ is jumping to another address if operands while comparing were equal to each other, or, if result of last computation was 0, or if Z flag is 1. Same thing as JZ in x86. Everything else is simple: execution flow is forking into two branches, then the branches are converging at the point where 0 is written into the R0, as a value returned from the function, and then function finishing. 8(PowerPC, ARM) Branch if Equal 53 CHAPTER 7. ACCESSING PASSED ARGUMENTS Chapter 7 Accessing passed arguments Now we figured out the caller function passing arguments to the callee via stack. But how callee access them? Listing 7.1: simple example #include int f (int a, int b, int c) { return a*b+c; }; int main() { printf ("%d\n", f(1, 2, 3)); return 0; }; 7.1 x86 7.1.1 MSVC What we have a er compilation (MSVC 2010 Express): Listing 7.2: MSVC 2010 Express _TEXT SEGMENT _a$ = 8 ; size = 4 _b$ = 12 ; size = 4 _c$ = 16 ; size = 4 _f PROC push ebp mov ebp, esp mov eax, DWORD PTR _a$[ebp] imul eax, DWORD PTR _b$[ebp] add eax, DWORD PTR _c$[ebp] pop ebp ret 0 _f ENDP _main PROC push ebp mov ebp, esp push 3 ; 3rd argument push 2 ; 2nd argument push 1 ; 1st argument call _f add esp, 12 54 7.1. X86 CHAPTER 7. ACCESSING PASSED ARGUMENTS push eax push OFFSET $SG2463 ; ’%d’, 0aH, 00H call _printf add esp, 8 ; return 0 xor eax, eax pop ebp ret 0 _main ENDP What we see is the 3 numbers are pushing to stack in function main() and f(int,int,int) is called then. Argument access inside f() is organized with the help of macros like: _a$ = 8, in the same way as local variables accessed, but the dierence in that these osets are positive (addressed with plus sign). So, adding _a$ macro to the value in the EBP register, outer side of stack frame is addressed. Then a value is stored into EAX. A er IMUL instruction execution, value in the EAX is a product1of value in EAX and what is stored in _b. A er IMUL execution, ADD is summing value in EAX and what is stored in _c. Value in the EAX is not needed to be moved: it is already in place it must be. Now return to caller —it will take value from the EAX and used it as printf() argument. 7.1.2 MSVC + OllyDbg Let’s illustrate this in OllyDbg. When we trace until the very first instruction in f() that uses one of the arguments (first one), we see that EBP is pointing to the stack frame, I marked its begin with red arrow. The first element of stack frame is saved EBP value, second is RA, third is first function argument, then second argument and third one. To access the first function argument, one need to add exactly 8 (2 32-bit words) to EBP. Figure 7.1: OllyDbg: inside of f() function 7.1.3 GCC Let’s compile the same in GCC 4.4.1 and let’s see results in IDA: Listing 7.3: GCC 4.4.1 public f f proc near arg_0 = dword ptr 8 1result of multiplication 55 7.2. X64 CHAPTER 7. ACCESSING PASSED ARGUMENTS arg_4 = dword ptr 0Ch arg_8 = dword ptr 10h push ebp mov ebp, esp mov eax, [ebp+arg_0] ; 1st argument imul eax, [ebp+arg_4] ; 2nd argument add eax, [ebp+arg_8] ; 3rd argument pop ebp retn f endp public main main proc near var_10 = dword ptr -10h var_C = dword ptr -0Ch var_8 = dword ptr -8 push ebp mov ebp, esp and esp, 0FFFFFFF0h sub esp, 10h mov [esp+10h+var_8], 3 ; 3rd argument mov [esp+10h+var_C], 2 ; 2nd argument mov [esp+10h+var_10], 1 ; 1st argument call f mov edx, offset aD ; "%d\n" mov [esp+10h+var_C], eax mov [esp+10h+var_10], edx call _printf mov eax, 0 leave retn main endp Almost the same result. The stack pointer is not returning back a er both function exeuction, because penultimate LEAVE (B.6.2) instruction will do this, at the end. 7.2 x64 The story is a bit dierent in x86-64, function arguments (4 or 6) are passed in registers, and a callee reading them from there instead of stack accessing. 7.2.1 MSVC Optimizing MSVC: Listing 7.4: MSVC 2012 /Ox x64 $SG2997 DB ’%d’, 0aH, 00H main PROC sub rsp, 40 mov edx, 2 lea r8d, QWORD PTR [rdx+1] ; R8D=3 lea ecx, QWORD PTR [rdx-1] ; ECX=1 call f lea rcx, OFFSET FLAT:$SG2997 ; ’%d’ mov edx, eax 56 7.2. X64 CHAPTER 7. ACCESSING PASSED ARGUMENTS call printf xor eax, eax add rsp, 40 ret 0 main ENDP f PROC ; ECX - 1st argument ; EDX - 2nd argument ; R8D - 3rd argument imul ecx, edx lea eax, DWORD PTR [r8+rcx] ret 0 f ENDP As we can see, very compact f() function takes arguments right from the registers. LEA instruction is used here for addi- tion, apparently, compiler considered this instruction here faster then ADD. LEA is also used in main() for the first and third arguments preparing, apparently, compiler thinks that it will work faster than usual value loading to the register using MOV instruction. Let’s try to take a look on output of non-optimizing MSVC: Listing 7.5: MSVC 2012 x64 f proc near ; shadow space: arg_0 = dword ptr 8 arg_8 = dword ptr 10h arg_10 = dword ptr 18h ; ECX - 1st argument ; EDX - 2nd argument ; R8D - 3rd argument mov [rsp+arg_10], r8d mov [rsp+arg_8], edx mov [rsp+arg_0], ecx mov eax, [rsp+arg_0] imul eax, [rsp+arg_8] add eax, [rsp+arg_10] retn f endp main proc near sub rsp, 28h mov r8d, 3 ; 3rd argument mov edx, 2 ; 2nd argument mov ecx, 1 ; 1st argument call f mov edx, eax lea rcx, $SG2931 ; "%d\n" call printf ; return 0 xor eax, eax add rsp, 28h retn main endp Somewhat puzzling: all 3 arguments from registers are saved to the stack for some reason. This is called “shadow space” 2: every Win64 may (but not required to) save all 4 register values there. This is done by two reasons: 1) it is too lavish to 2http://msdn.microsoft.com/en-us/library/zthk2dkh(v=vs.80).aspx 57 7.2. X64 CHAPTER 7. ACCESSING PASSED ARGUMENTS allocate the whole register (or even 4 registers) for the input argument, so it will be accessed via stack; 2) debugger is always aware where to find function arguments at a break 3. It is duty of caller to allocate “shadow space” in stack. 7.2.2 GCC Optimizing GCC does more or less understanable code: Listing 7.6: GCC 4.4.6 -O3 x64 f: ; EDI - 1st argument ; ESI - 2nd argument ; EDX - 3rd argument imul esi, edi lea eax, [rdx+rsi] ret main: sub rsp, 8 mov edx, 3 mov esi, 2 mov edi, 1 call f mov edi, OFFSET FLAT:.LC0 ; "%d\n" mov esi, eax xor eax, eax ; number of vector registers passed call printf xor eax, eax add rsp, 8 ret Non-optimizing GCC: Listing 7.7: GCC 4.4.6 x64 f: ; EDI - 1st argument ; ESI - 2nd argument ; EDX - 3rd argument push rbp mov rbp, rsp mov DWORD PTR [rbp-4], edi mov DWORD PTR [rbp-8], esi mov DWORD PTR [rbp-12], edx mov eax, DWORD PTR [rbp-4] imul eax, DWORD PTR [rbp-8] add eax, DWORD PTR [rbp-12] leave ret main: push rbp mov rbp, rsp mov edx, 3 mov esi, 2 mov edi, 1 call f mov edx, eax mov eax, OFFSET FLAT:.LC0 ; "%d\n" mov esi, edx mov rdi, rax mov eax, 0 ; number of vector registers passed 3http://msdn.microsoft.com/en-us/library/ew5tede7(v=VS.90).aspx 58 7.3. ARM CHAPTER 7. ACCESSING PASSED ARGUMENTS call printf mov eax, 0 leave ret There are no “shadow space” requirement in System V *NIX [21], but callee may need to save arguments somewhere, because, again, it may be regsiters shortage. 7.2.3 GCC: uint64_t instead int Our example worked with 32-bit int, that is why 32-bit register parts were used (prefixed by E-). It can be altered slightly in order to use 64-bit values: #include #include uint64_t f (uint64_t a, uint64_t b, uint64_t c) { return a*b+c; }; int main() { printf ("%lld\n", f(0x1122334455667788, 0x1111111122222222, 0x3333333344444444)); return 0; }; Listing 7.8: GCC 4.4.6 -O3 x64 f proc near imul rsi, rdi lea rax, [rdx+rsi] retn f endp main proc near sub rsp, 8 mov rdx, 3333333344444444h ; 3rd argument mov rsi, 1111111122222222h ; 2nd argument mov rdi, 1122334455667788h ; 1st argument call f mov edi, offset format ; "%lld\n" mov rsi, rax xor eax, eax ; number of vector registers passed call _printf xor eax, eax add rsp, 8 retn main endp The code is very same, but registers (prefixed by R-) are used as a whole. 7.3 ARM 7.3.1 Non-optimizing Keil + ARM mode .text:000000A4 00 30 A0 E1 MOV R3, R0 .text:000000A8 93 21 20 E0 MLA R0, R3, R1, R2 .text:000000AC 1E FF 2F E1 BX LR 59 7.3. ARM CHAPTER 7. ACCESSING PASSED ARGUMENTS ... .text:000000B0 main .text:000000B0 10 40 2D E9 STMFD SP!, {R4,LR} .text:000000B4 03 20 A0 E3 MOV R2, #3 .text:000000B8 02 10 A0 E3 MOV R1, #2 .text:000000BC 01 00 A0 E3 MOV R0, #1 .text:000000C0 F7 FF FF EB BL f .text:000000C4 00 40 A0 E1 MOV R4, R0 .text:000000C8 04 10 A0 E1 MOV R1, R4 .text:000000CC 5A 0F 8F E2 ADR R0, aD_0 ; "%d\n" .text:000000D0 E3 18 00 EB BL __2printf .text:000000D4 00 00 A0 E3 MOV R0, #0 .text:000000D8 10 80 BD E8 LDMFD SP!, {R4,PC} In main() function, two other functions are simply called, and three values are passed to the first one (f). As I mentioned before, in ARM, first 4 values are usually passed in first 4 registers (R0-R3). ffunction, as it seems, use first 3 registers (R0-R2) as arguments. MLA (Multiply Accumulate) instruction multiplicates two first operands (R3 and R1), adds third operand (R2) to product and places result into zeroth operand (R0), via which, by standard, values are returned from functions. Multiplication and addition at once4 (Fused multiply–add) is very useful operation, by the way, there is no such instruction in x86, if not to count new FMA-instruction5 in SIMD. The very first MOV R3, R0, instruction, apparently, redundant (single MLA instruction could be used here instead), com- piler was not optimized it, since this is non-optimizing compilation. BX instruction returns control to the address stored in theLR register and, if it is necessary, switches processor mode from thumb to ARM or vice versa. This can be necessary since, as we can see, f function is not aware, from which code it may be called, from ARM or thumb. This, if it will be called from thumb code, BX will not only return control to the calling function, but also will switch processor mode to thumb mode. Or not switch, if the function was called from ARM code. 7.3.2 Optimizing Keil + ARM mode .text:00000098 f .text:00000098 91 20 20 E0 MLA R0, R1, R0, R2 .text:0000009C 1E FF 2F E1 BX LR And here is f function compiled by Keil compiler in full optimization mode (-O3). MOV instruction was optimized (or re- duced) and now MLA uses all input registers and also places result right into R0, exactly where calling function will read it and use. 7.3.3 Optimizing Keil + thumb mode .text:0000005E 48 43 MULS R0, R1 .text:00000060 80 18 ADDS R0, R0, R2 .text:00000062 70 47 BX LR MLA instruction is not available in thumb mode, so, compiler generates the code doing these two operations separately. First MULS instruction multiply R0 by R1 leaving result in the R1 register. Second (ADDS) instruction adds result and R2 leaving result in the R0 register. 4wikipedia: Multiply–accumulate operation 5https://en.wikipedia.org/wiki/FMA_instruction_set 60 CHAPTER 8. ONE MORE WORD ABOUT RESULTS RETURNING. Chapter 8 One more word about results returning. As of x86, function execution result is usually returned 1 in the EAX register. If it is byte type or character (char) —then in the lowest register EAX part —AL. If function returns float number, the FPU register ST(0) is to be used instead. In ARM, result is usually returned in the R0 register. By the way, what if returning value of the main() function will be declared not as int but as void? so-called startup-code is calling main() roughly as: push envp push argv push argc call main push eax call exit In other words: exit(main(argc,argv,envp)); If you declare main() as void and nothing will be returned explicitly (by return statement), then something random, that was stored in the EAX register at the moment of the main() finish, will come into the sole exit() function argument. Most likely, there will be a random value, leaved from your function execution. So, exit code of program will be pseudorandom. I can illustrate this fact. Please notice, the main() function has void type: #include void main() { printf ("Hello, world!\n"); }; Let’s compile it in Linux. GCC 4.8.1 replaced printf() to puts() (we saw this before: 2.3.3), but that’s OK, since puts() returns number of char- acters printed, just like printf(). Please notice that EAX is not zeroed before main() finish. This means, EAX value at the main() finish will contain what puts() leaved there. Listing 8.1: GCC 4.8.1 .LC0: .string "Hello, world!" main: push ebp mov ebp, esp and esp, -16 sub esp, 16 mov DWORD PTR [esp], OFFSET FLAT:.LC0 call puts 1See also: MSDN: Return Values (C++): http://msdn.microsoft.com/en-us/library/7572ztz4.aspx 61 CHAPTER 8. ONE MORE WORD ABOUT RESULTS RETURNING. leave ret Let’ s write bash script, showing exit status: Listing 8.2: tst.sh #!/bin/sh ./hello_world echo $? And run it: $ tst.sh Hello, world! 14 14 is a number of characters printed. Let’s back to the fact the returning value is leaved in the EAX register. That is why old C compilers cannot create functions capable of returning something not fitting in one register (usually type int) but if one needs it, one should return information via pointers passed in function arguments. Now it is possible, to return, let’s say, whole structure, but still it is not very pop- ular. If function must return a large structure, caller must allocate it and pass pointer to it via first argument, transparently for programmer. That is almost the same as to pass pointer in first argument manually, but compiler hide this. Small example: struct s { int a; int b; int c; }; struct s get_some_values (int a) { struct s rt; rt.a=a+1; rt.b=a+2; rt.c=a+3; return rt; }; ...what we got (MSVC 2010 /Ox): $T3853 = 8 ; size = 4 _a$ = 12 ; size = 4 ?get_some_values@@YA?AUs@@H@Z PROC ; get_some_values mov ecx, DWORD PTR _a$[esp-4] mov eax, DWORD PTR $T3853[esp-4] lea edx, DWORD PTR [ecx+1] mov DWORD PTR [eax], edx lea edx, DWORD PTR [ecx+2] add ecx, 3 mov DWORD PTR [eax+4], edx mov DWORD PTR [eax+8], ecx ret 0 ?get_some_values@@YA?AUs@@H@Z ENDP ; get_some_values Macro name for internal variable passing pointer to structure is $T3853 here. This example can be rewritten using C99 language extensions: struct s { 62 CHAPTER 8. ONE MORE WORD ABOUT RESULTS RETURNING. int a; int b; int c; }; struct s get_some_values (int a) { return (struct s){.a=a+1, .b=a+2, .c=a+3}; }; Listing 8.3: GCC 4.8.1 _get_some_values proc near ptr_to_struct = dword ptr 4 a = dword ptr 8 mov edx, [esp+a] mov eax, [esp+ptr_to_struct] lea ecx, [edx+1] mov [eax], ecx lea ecx, [edx+2] add edx, 3 mov [eax+4], ecx mov [eax+8], edx retn _get_some_values endp As we may see, the function is just filling fields in the structure, allocated by caller function. So there are no performance drawbacks. 63 CHAPTER 9. POINTERS Chapter 9 Pointers Pointers are o en used to return values from function (recall scanf() case (6)). For example, when function should return two values. 9.1 Global variables example #include void f1 (int x, int y, int *sum, int *product) { *sum=x+y; *product=x*y; }; int sum, product; void main() { f1(123, 456, &sum, &product); printf ("sum=%d, product=%d\n", sum, product); }; This compiling into: Listing 9.1: Optimizing MSVC 2010 (/Ox /Ob0) COMM _product:DWORD COMM _sum:DWORD $SG2803 DB ’sum=%d, product=%d’, 0aH, 00H _x$ = 8 ; size = 4 _y$ = 12 ; size = 4 _sum$ = 16 ; size = 4 _product$ = 20 ; size = 4 _f1 PROC mov ecx, DWORD PTR _y$[esp-4] mov eax, DWORD PTR _x$[esp-4] lea edx, DWORD PTR [eax+ecx] imul eax, ecx mov ecx, DWORD PTR _product$[esp-4] push esi mov esi, DWORD PTR _sum$[esp] mov DWORD PTR [esi], edx mov DWORD PTR [ecx], eax pop esi ret 0 _f1 ENDP 64 9.1. GLOBAL VARIABLES EXAMPLE CHAPTER 9. POINTERS _main PROC push OFFSET _product push OFFSET _sum push 456 ; 000001c8H push 123 ; 0000007bH call _f1 mov eax, DWORD PTR _product mov ecx, DWORD PTR _sum push eax push ecx push OFFSET $SG2803 call DWORD PTR __imp__printf add esp, 28 ; 0000001cH xor eax, eax ret 0 _main ENDP Let’s see this in OllyDbg: fig. 9.1. At first, global variables addresses are passed intof1(). We can click “Follow in dump” on the stack element, and we will see a place in data segment allocated for two variables. These variables are cleared, because non-initialized data (BSS1) are cleared before execution begin. They are residing in data segment, we can be sure it is so, by pressing Alt-M and seeing memory map: fig. 9.5. Let’s trace (F7) until execution of f1()fig. 9.2. Two values are seen in the stack 456 (0x1C8) and 123 (0x7B), and two global variables addresses as well. Let’s trace until the end of f1(). At the window at le we see how calculation results are appeared in the gloval variables fig. 9.3. Now values of global variables are loaded into registers for passing into printf(): fig. 9.4. Figure 9.1: OllyDbg: global variables addresses are passing into f1() 1Block Started by Symbol 65 9.1. GLOBAL VARIABLES EXAMPLE CHAPTER 9. POINTERS Figure 9.2: OllyDbg: f1()is started Figure 9.3: OllyDbg: f1()finishes 66 9.2. LOCAL VARIABLES EXAMPLE CHAPTER 9. POINTERS Figure 9.4: OllyDbg: global variables addresses are passed into printf() Figure 9.5: OllyDbg: memory map 9.2 Local variables example Let’s rework our example slightly: Listing 9.2: now variables are local void main() { int sum, product; // now variables are here f1(123, 456, &sum, &product); printf ("sum=%d, product=%d\n", sum, product); }; f1()function code will not changed. Only main() code will: Listing 9.3: Optimizing MSVC 2010 (/Ox /Ob0) _product$ = -8 ; size = 4 _sum$ = -4 ; size = 4 _main PROC ; Line 10 sub esp, 8 ; Line 13 67 9.2. LOCAL VARIABLES EXAMPLE CHAPTER 9. POINTERS lea eax, DWORD PTR _product$[esp+8] push eax lea ecx, DWORD PTR _sum$[esp+12] push ecx push 456 ; 000001c8H push 123 ; 0000007bH call _f1 ; Line 14 mov edx, DWORD PTR _product$[esp+24] mov eax, DWORD PTR _sum$[esp+24] push edx push eax push OFFSET $SG2803 call DWORD PTR __imp__printf ; Line 15 xor eax, eax add esp, 36 ; 00000024H ret 0 Let’s again take a look into OllyDbg. Local variable addresses in the stack are 0x35FCF4 and 0x35FCF8. We see how these are pushed into the stack: fig. 9.6. f1()is started. Random garbage are at 0x35FCF4 and 0x35FCF8 so far fig. 9.7. f1()finished. There are 0xDB18 and 0x243 now at 0x35FCF4 and 0x35FCF8 addresses, these values are f1()function result. Figure 9.6: OllyDbg: addresses of local variables are pushed into the stack 68 9.3. CONCLUSION CHAPTER 9. POINTERS Figure 9.7: OllyDbg: f1()starting Figure 9.8: OllyDbg: f1()finished 9.3 Conclusion f1()can return results to any place in memory, located anywhere. This is essence and usefulness of pointers. By the way, C++ references works just in the same way. Read more about them: (29.3). 69 CHAPTER 10. CONDITIONAL JUMPS Chapter 10 Conditional jumps Now about conditional jumps. #include void f_signed (int a, int b) { if (a>b) printf ("a>b\n"); if (a==b) printf ("a==b\n"); if (ab) printf ("a>b\n"); if (a==b) printf ("a==b\n"); if (ab’ call _printf add esp, 4 $LN3@f_signed: mov ecx, DWORD PTR _a$[ebp] cmp ecx, DWORD PTR _b$[ebp] jne SHORT $LN2@f_signed push OFFSET $SG739 ; ’a==b’ call _printf add esp, 4 $LN2@f_signed: mov edx, DWORD PTR _a$[ebp] cmp edx, DWORD PTR _b$[ebp] jge SHORT $LN4@f_signed push OFFSET $SG741 ; ’ab’ call _printf add esp, 4 $LN3@f_unsigned: mov ecx, DWORD PTR _a$[ebp] cmp ecx, DWORD PTR _b$[ebp] jne SHORT $LN2@f_unsigned push OFFSET $SG2763 ; ’a==b’ call _printf add esp, 4 $LN2@f_unsigned: mov edx, DWORD PTR _a$[ebp] cmp edx, DWORD PTR _b$[ebp] jae SHORT $LN4@f_unsigned push OFFSET $SG2765 ; ’ab" jmp puts .L1: rep ret .L7: mov DWORD PTR [esp+4], OFFSET FLAT:.LC1 ; "a==b" jmp puts 76 10.2. ARM CHAPTER 10. CONDITIONAL JUMPS We also see JMP puts here instead of CALL puts / RETN. This kind of trick will be described later: 11.1.1. Needless to say, that type of x86 code is rare. MSVC 2012, as it seems, can’t do that. On the other case, assembly language programmers are fully aware of the fact that Jcc instructions can be stacked. So if you see it somewhere, it may be a good probability that the code is hand-written. f_unsigned() function is not that æsthetically short: Listing 10.5: GCC 4.8.1 f_unsigned() f_unsigned: push esi push ebx sub esp, 20 mov esi, DWORD PTR [esp+32] mov ebx, DWORD PTR [esp+36] cmp esi, ebx ja .L13 cmp esi, ebx ; instruction may be removed je .L14 .L10: jb .L15 add esp, 20 pop ebx pop esi ret .L15: mov DWORD PTR [esp+32], OFFSET FLAT:.LC2 ; "ab" call puts cmp esi, ebx jne .L10 .L14: mov DWORD PTR [esp+32], OFFSET FLAT:.LC1 ; "a==b" add esp, 20 pop ebx pop esi jmp puts So, optimization algorithms of GCC 4.8.1 are probably not always perfect yet. 10.2 ARM 10.2.1 Optimizing Keil + ARM mode Listing 10.6: Optimizing Keil + ARM mode .text:000000B8 EXPORT f_signed .text:000000B8 f_signed ; CODE XREF: main+C .text:000000B8 70 40 2D E9 STMFD SP!, {R4-R6,LR} .text:000000BC 01 40 A0 E1 MOV R4, R1 .text:000000C0 04 00 50 E1 CMP R0, R4 .text:000000C4 00 50 A0 E1 MOV R5, R0 .text:000000C8 1A 0E 8F C2 ADRGT R0, aAB ; "a>b\n" .text:000000CC A1 18 00 CB BLGT __2printf .text:000000D0 04 00 55 E1 CMP R5, R4 .text:000000D4 67 0F 8F 02 ADREQ R0, aAB_0 ; "a==b\n" .text:000000D8 9E 18 00 0B BLEQ __2printf .text:000000DC 04 00 55 E1 CMP R5, R4 77 10.2. ARM CHAPTER 10. CONDITIONAL JUMPS .text:000000E0 70 80 BD A8 LDMGEFD SP!, {R4-R6,PC} .text:000000E4 70 40 BD E8 LDMFD SP!, {R4-R6,LR} .text:000000E8 19 0E 8F E2 ADR R0, aAB_1 ; "ab\n”, into R0 and BLGT calls printf(). Consequently, these instructions with -GT suix, will be executed only in the case when value in the R0 (푎 is there) was bigger than value in the R4 (푏 is there). Then we see ADREQ and BLEQ instructions. They behave just like ADR and BL but is to be executed only in the case when operands were equal to each other while comparison. Another CMP is before them (since printf() call may tamper state of flags). Then we see LDMGEFD, this instruction works just like LDMFD1, but will be triggered only in the case when one value was greater or equal to another while comparison (Greater or Equal). The sense of “LDMGEFD SP!, {R4-R6,PC}” instruction is that is like function epilogue, but it will be triggered only if 푎 >= 푏, only then function execution will be finished. But if it is not true, i.e., 푎 < 푏, then control flow come to next “LDMFD SP!, {R4-R6,LR}” instruction, this is one more function epilogue, this instruction restores R4-R6 registers state, but also LR instead ofPC, thus, it does not returns from function. Last two instructions calls printf() with the string «ab\n" .text:0000007E 06 F0 B7 F8 BL __2printf .text:00000082 .text:00000082 loc_82 ; CODE XREF: f_signed+8 .text:00000082 A5 42 CMP R5, R4 .text:00000084 02 D1 BNE loc_8C .text:00000086 A4 A0 ADR R0, aAB_0 ; "a==b\n" .text:00000088 06 F0 B2 F8 BL __2printf .text:0000008C .text:0000008C loc_8C ; CODE XREF: f_signed+12 .text:0000008C A5 42 CMP R5, R4 .text:0000008E 02 DA BGE locret_96 .text:00000090 A3 A0 ADR R0, aAB_1 ; "a void f(int i) { printf ("f(%d)\n", i); }; int main() { int i; for (i=2; i<10; i++) f(i); return 0; }; Result (MSVC 2010): Listing 12.1: MSVC 2010 _i$ = -4 _main PROC push ebp mov ebp, esp push ecx mov DWORD PTR _i$[ebp], 2 ; loop initialization jmp SHORT $LN3@main 89 12.1. X86 CHAPTER 12. LOOPS $LN2@main: mov eax, DWORD PTR _i$[ebp] ; here is what we do after each iteration: add eax, 1 ; add 1 to i value mov DWORD PTR _i$[ebp], eax $LN3@main: cmp DWORD PTR _i$[ebp], 10 ; this condition is checked *before* each iteration jge SHORT $LN1@main ; if i is biggest or equals to 10, let’s finish loop mov ecx, DWORD PTR _i$[ebp] ; loop body: call f(i) push ecx call _f add esp, 4 jmp SHORT $LN2@main ; jump to loop begin $LN1@main: ; loop end xor eax, eax mov esp, ebp pop ebp ret 0 _main ENDP Nothing very special, as we see. GCC 4.4.1 emits almost the same code, with one subtle dierence: Listing 12.2: GCC 4.4.1 main proc near ; DATA XREF: _start+17 var_20 = dword ptr -20h var_4 = dword ptr -4 push ebp mov ebp, esp and esp, 0FFFFFFF0h sub esp, 20h mov [esp+20h+var_4], 2 ; i initializing jmp short loc_8048476 loc_8048465: mov eax, [esp+20h+var_4] mov [esp+20h+var_20], eax call f add [esp+20h+var_4], 1 ; i increment loc_8048476: cmp [esp+20h+var_4], 9 jle short loc_8048465 ; if i<=9, continue loop mov eax, 0 leave retn main endp Now let’s see what we will get if optimization is turned on (/Ox): Listing 12.3: Optimizing MSVC _main PROC push esi mov esi, 2 $LL3@main: push esi call _f inc esi add esp, 4 cmp esi, 10 ; 0000000aH jl SHORT $LL3@main 90 12.1. X86 CHAPTER 12. LOOPS xor eax, eax pop esi ret 0 _main ENDP What is going on here is: space for the i variable is not allocated in local stack anymore, but even individual register: the ESI. This is possible in such small functions where not so many local variables are present. One very important property is the f() function must not change the value in the ESI. Our compiler is sure here. And if compiler decided to use the ESI register in f() too, its value would be saved then at the f() function’s prologue and restored at the f() function’s epilogue. Almost like in our listing: please note PUSH ESI/POP ESI at the function begin and end. Let’s try GCC 4.4.1 with maximal optimization turned on (-O3 option): Listing 12.4: Optimizing GCC 4.4.1 main proc near var_10 = dword ptr -10h push ebp mov ebp, esp and esp, 0FFFFFFF0h sub esp, 10h mov [esp+10h+var_10], 2 call f mov [esp+10h+var_10], 3 call f mov [esp+10h+var_10], 4 call f mov [esp+10h+var_10], 5 call f mov [esp+10h+var_10], 6 call f mov [esp+10h+var_10], 7 call f mov [esp+10h+var_10], 8 call f mov [esp+10h+var_10], 9 call f xor eax, eax leave retn main endp Huh, GCC just unwind our loop. Loop unwinding has advantage in these cases when there is not so much iterations and we could economy some execution speed by removing all loop supporting instructions. On the other side, resulting code is obviously larger. OK, let’s increase maximal value of the i variable to 100 and try again. GCC resulting: Listing 12.5: GCC public main main proc near var_20 = dword ptr -20h push ebp mov ebp, esp and esp, 0FFFFFFF0h push ebx mov ebx, 2 ; i=2 sub esp, 1Ch nop ; aligning label loc_80484D0 (loop body begin) by 16-byte border loc_80484D0: 91 12.1. X86 CHAPTER 12. LOOPS mov [esp+20h+var_20], ebx ; pass i as first argument to f() add ebx, 1 ; i++ call f cmp ebx, 64h ; i==100? jnz short loc_80484D0 ; if not, continue add esp, 1Ch xor eax, eax ; return 0 pop ebx mov esp, ebp pop ebp retn main endp It is quite similar to what MSVC 2010 with optimization (/Ox) produce. With the exception the EBX register will be fixed to the i variable. GCC is sure this register will not be modified inside of the f() function, and if it will, it will be saved at the function prologue and restored at epilogue, just like here in the main() function. 12.1.1 OllyDbg Let’s compile our example in MSVC 2010 with /Ox and /Ob0 options and load it into OllyDbg. It seems, OllyDbg is able to detect simple loops and show them in square brackets, for convenience: fig. 12.1. By tracing (F8 (step over)) we see how ESI incrementing. Here, for instance, ESI =i=6: fig. 12.2. 9 is a last loop value. That’s why JL will not trigger a er increment, and function finishing: fig. 12.3. Figure 12.1: OllyDbg: main() begin Figure 12.2: OllyDbg: loop body just executed with i=6 92 12.1. X86 CHAPTER 12. LOOPS Figure 12.3: OllyDbg: ESI =10, loop end 12.1.2 tracer As we might see, it is not very convenient to trace in debugger manually. That’s one of the reasons I write tracer for myself. I open compiled example in IDA, I find the address of the instruction PUSH ESI (passing sole argument into f()) and this is 0x401026 for me and I run tracer: tracer.exe -l:loops_2.exe bpx=loops_2.exe!0x00401026 BPX just sets breakpoint at address and then will print registers state. In the tracer.log I see a er running: PID=12884|New process loops_2.exe (0) loops_2.exe!0x401026 EAX=0x00a328c8 EBX=0x00000000 ECX=0x6f0f4714 EDX=0x00000000 ESI=0x00000002 EDI=0x00333378 EBP=0x0024fbfc ESP=0x0024fbb8 EIP=0x00331026 FLAGS=PF ZF IF (0) loops_2.exe!0x401026 EAX=0x00000005 EBX=0x00000000 ECX=0x6f0a5617 EDX=0x000ee188 ESI=0x00000003 EDI=0x00333378 EBP=0x0024fbfc ESP=0x0024fbb8 EIP=0x00331026 FLAGS=CF PF AF SF IF (0) loops_2.exe!0x401026 EAX=0x00000005 EBX=0x00000000 ECX=0x6f0a5617 EDX=0x000ee188 ESI=0x00000004 EDI=0x00333378 EBP=0x0024fbfc ESP=0x0024fbb8 EIP=0x00331026 FLAGS=CF PF AF SF IF (0) loops_2.exe!0x401026 EAX=0x00000005 EBX=0x00000000 ECX=0x6f0a5617 EDX=0x000ee188 ESI=0x00000005 EDI=0x00333378 EBP=0x0024fbfc ESP=0x0024fbb8 EIP=0x00331026 FLAGS=CF AF SF IF (0) loops_2.exe!0x401026 EAX=0x00000005 EBX=0x00000000 ECX=0x6f0a5617 EDX=0x000ee188 ESI=0x00000006 EDI=0x00333378 EBP=0x0024fbfc ESP=0x0024fbb8 EIP=0x00331026 FLAGS=CF PF AF SF IF (0) loops_2.exe!0x401026 EAX=0x00000005 EBX=0x00000000 ECX=0x6f0a5617 EDX=0x000ee188 ESI=0x00000007 EDI=0x00333378 EBP=0x0024fbfc ESP=0x0024fbb8 EIP=0x00331026 FLAGS=CF AF SF IF (0) loops_2.exe!0x401026 EAX=0x00000005 EBX=0x00000000 ECX=0x6f0a5617 EDX=0x000ee188 ESI=0x00000008 EDI=0x00333378 EBP=0x0024fbfc ESP=0x0024fbb8 EIP=0x00331026 FLAGS=CF AF SF IF 93 12.1. X86 CHAPTER 12. LOOPS (0) loops_2.exe!0x401026 EAX=0x00000005 EBX=0x00000000 ECX=0x6f0a5617 EDX=0x000ee188 ESI=0x00000009 EDI=0x00333378 EBP=0x0024fbfc ESP=0x0024fbb8 EIP=0x00331026 FLAGS=CF PF AF SF IF PID=12884|Process loops_2.exe exited. ExitCode=0 (0x0) We see how value of ESI register is changed from 2 to 9. Even more than that, tracer can collect register values on all addresses within function. This is called trace there. Each instruction is being traced, all interesting register values are noticed and collected. .idc-script for IDA is then generated. So, in the IDA I’ve learned that main() function address is 0x00401020 and I run: tracer.exe -l:loops_2.exe bpf=loops_2.exe!0x00401020,trace:cc BPF mean set breakpoint on function. As a result, I have got loops_2.exe.idc and loops_2.exe_clear.idc scripts. I’m loading loops_2.exe.idc into IDA and I see: fig. 12.4 We see that ESI can be from 2 to 9 at the begin of loop body, but from 3 to 0xA (10) a er increment. We can also see that main() is finishing with 0 in EAX. tracer also generates loops_2.exe.txt, containing information about how many times each instruction was executed and register values: Listing 12.6: loops_2.exe.txt 0x401020 (.text+0x20), e= 1 [PUSH ESI] ESI=1 0x401021 (.text+0x21), e= 1 [MOV ESI, 2] 0x401026 (.text+0x26), e= 8 [PUSH ESI] ESI=2..9 0x401027 (.text+0x27), e= 8 [CALL 8D1000h] tracing nested maximum level (1) reached, ⤦ Ç skipping this CALL 8D1000h=0x8d1000 0x40102c (.text+0x2c), e= 8 [INC ESI] ESI=2..9 0x40102d (.text+0x2d), e= 8 [ADD ESP, 4] ESP=0x38fcbc 0x401030 (.text+0x30), e= 8 [CMP ESI, 0Ah] ESI=3..0xa 0x401033 (.text+0x33), e= 8 [JL 8D1026h] SF=false,true OF=false 0x401035 (.text+0x35), e= 1 [XOR EAX, EAX] 0x401037 (.text+0x37), e= 1 [POP ESI] 0x401038 (.text+0x38), e= 1 [RETN] EAX=0 grep can be used here. Figure 12.4: IDA with .idc-script loaded 94 12.2. ARM CHAPTER 12. LOOPS 12.2 ARM 12.2.1 Non-optimizing Keil + ARM mode main STMFD SP!, {R4,LR} MOV R4, #2 B loc_368 loc_35C ; CODE XREF: main+1C MOV R0, R4 BL f ADD R4, R4, #1 loc_368 ; CODE XREF: main+8 CMP R4, #0xA BLT loc_35C MOV R0, #0 LDMFD SP!, {R4,PC} Iteration counter i is to be stored in the R4 register. “MOV R4, #2” instruction just initializing i. “MOV R0, R4” and“BL f”instructions are compose loop body, the first instruction preparing argument for f()function and the second is calling it. “ADD R4, R4, #1” instruction is just adding 1 to the i variable during each iteration. “CMP R4, #0xA” comparing i with 0xA (10). Next instruction BLT (Branch Less Than) will jump if i is less than 10. Otherwise, 0 will be written into R0 (since our function returns 0) and function execution ended. 12.2.2 Optimizing Keil + thumb mode _main PUSH {R4,LR} MOVS R4, #2 loc_132 ; CODE XREF: _main+E MOVS R0, R4 BL example7_f ADDS R4, R4, #1 CMP R4, #0xA BLT loc_132 MOVS R0, #0 POP {R4,PC} Practically, the same. 12.2.3 Optimizing Xcode (LLVM) + thumb-2 mode _main PUSH {R4,R7,LR} MOVW R4, #0x1124 ; "%d\n" MOVS R1, #2 MOVT.W R4, #0 ADD R7, SP, #4 ADD R4, PC MOV R0, R4 BLX _printf MOV R0, R4 MOVS R1, #3 BLX _printf MOV R0, R4 MOVS R1, #4 95 12.3. ONE MORE THING CHAPTER 12. LOOPS BLX _printf MOV R0, R4 MOVS R1, #5 BLX _printf MOV R0, R4 MOVS R1, #6 BLX _printf MOV R0, R4 MOVS R1, #7 BLX _printf MOV R0, R4 MOVS R1, #8 BLX _printf MOV R0, R4 MOVS R1, #9 BLX _printf MOVS R0, #0 POP {R4,R7,PC} In fact, this was in my f() function: void f(int i) { // do something here printf ("%d\n", i); }; So, LLVM not just unrolled the loop, but also represented my very simple function f() as inlined, and inserted its body 8 times instead of loop. This is possible when function is so primitive (like mine) and when it is called not many times (like here). 12.3 One more thing On the code generated we can see: a er iinitialization, loop body will not be executed, but i condition checked first, and only a er loop body is to be executed. And that is correct. Because, if loop condition is not met at the beginning, loop body must not be executed. For example, this is possible in the following case: for (i=0; i pointer to the string mov eax, edx ; move to EAX $LL2@strlen: mov cl, BYTE PTR [eax] ; CL = *EAX inc eax ; EAX++ test cl, cl ; CL==0? jne SHORT $LL2@strlen ; no, continue loop sub eax, edx ; calculate pointers difference dec eax ; decrement EAX ret 0 _strlen ENDP Now it is all simpler. But it is needless to say the compiler could use registers such eiciently only in small functions with small number of local variables. INC/DEC—are increment/decrement instruction, in other words: add 1 to variable or subtract. 13.1.4 Optimizing MSVC + OllyDbg We may try this (optimized) example in OllyDbg. Here is a very first iteration: fig. 13.1. We see that OllyDbg found a loop and, for convenience, wrapped its instructions in bracket. By clicking right button on EAX, we can choose “Follow in Dump” and the memory window position will scroll to the right place. We can see here a string “hello!” in memory. There are at least once zero byte a er it and then random garbage. If OllyDbg sees that a register has an address pointing to a string, it will show it. Let’s press F8 (step over) enough time so the current address will be at the loop body begin again: fig. 13.2. We see that EAX contain address of the second character in the string. We will press F8 enough times in order to escape from the loop: fig. 13.3. We will see that EAX now contain address of zeroth byte, placed right a er the string. Meanwhile, EDX wasn’t changed, so it still pointing to the string begin. Dierence between these two addresses will be calculated now. SUB instruction was just executed: fig. 13.4. Dierence in the EAX—7. Indeed, the “hello!” string length—6, but with ze- roth byte included—7. But the strlen() must return non-zero characters in the string. So the decrement will processed now and then return from the function. 99 13.1. X86 CHAPTER 13. STRLEN() Figure 13.1: OllyDbg: first iteration begin Figure 13.2: OllyDbg: second iteration begin Figure 13.3: OllyDbg: pointers dierence to be calculated now 100 13.1. X86 CHAPTER 13. STRLEN() Figure 13.4: OllyDbg: EAX to be decremented now 13.1.5 Optimizing GCC Let’s check GCC 4.4.1 with optimization turned on (-O3 key): public strlen strlen proc near arg_0 = dword ptr 8 push ebp mov ebp, esp mov ecx, [ebp+arg_0] mov eax, ecx loc_8048418: movzx edx, byte ptr [eax] add eax, 1 test dl, dl jnz short loc_8048418 not ecx add eax, ecx pop ebp retn strlen endp Here GCC is almost the same as MSVC, except of MOVZX presence. However, MOVZX could be replaced here to mov dl, byte ptr [eax]. Probably, it is simpler for GCC compiler’s code generator to remember the whole register is allocated for char variable and it can be sure the highest bits will not contain any noise at any point. A er, we also see new instruction NOT. This instruction inverts all bits in operand. It can be said, it is synonym to the XOR ECX, 0ffffffffh instruction. NOT and following ADD calculating pointer dierence and subtracting 1. At the beginning ECX, where pointer to str is stored, inverted and 1 is subtracted from it. See also: “Signed number representations” (32). In other words, at the end of function, just a er loop body, these operations are executed: ecx=str; eax=eos; ecx=(-ecx)-1; eax=eax+ecx return eax ...and this is eectively equivalent to: ecx=str; eax=eos; eax=eax-ecx; 101 13.2. ARM CHAPTER 13. STRLEN() eax=eax-1; return eax Why GCC decided it would be better? I cannot be sure. But I’m sure the both variants are eectively equivalent in eiciency sense. 13.2 ARM 13.2.1 Non-optimizing Xcode (LLVM) + ARM mode Listing 13.2: Non-optimizing Xcode (LLVM) + ARM mode _strlen eos = -8 str = -4 SUB SP, SP, #8 ; allocate 8 bytes for local variables STR R0, [SP,#8+str] LDR R0, [SP,#8+str] STR R0, [SP,#8+eos] loc_2CB8 ; CODE XREF: _strlen+28 LDR R0, [SP,#8+eos] ADD R1, R0, #1 STR R1, [SP,#8+eos] LDRSB R0, [R0] CMP R0, #0 BEQ loc_2CD4 B loc_2CB8 loc_2CD4 ; CODE XREF: _strlen+24 LDR R0, [SP,#8+eos] LDR R1, [SP,#8+str] SUB R0, R0, R1 ; R0=eos-str SUB R0, R0, #1 ; R0=R0-1 ADD SP, SP, #8 ; deallocate 8 bytes for local variables BX LR Non-optimizing LLVM generates too much code, however, here we can see how function works with local variables in the stack. There are only two local variables in our function, eos and str. In this listing, generated by IDA, I renamed var_8 and var_4 into eos and str manually. So, first instructions are just saves input value in str and eos. Loop body is beginning at loc_2CB8 label. First three instruction in loop body (LDR, ADD, STR) loads eos value into R0, then value is incremented and it is saved back into eos local variable located in the stack. The next “LDRSB R0, [R0]” (Load Register Signed Byte) instruction loading byte from memory at R0 address and sign- extends it to 32-bit. This is similar to MOVSX (13.1.1) instruction in x86. The compiler treating this byte as signed since char type in C standard is signed. I already wrote about it (13.1.1) in this section, but related to x86. It is should be noted, it is impossible in ARM to use 8-bit part or 16-bit part of 32-bit register separately of the whole register, as it is in x86. Apparently, it is because x86 has a huge history of compatibility with its ancestors like 16-bit 8086 and even 8-bit 8080, but ARM was developed from scratch as 32-bit RISC-processor. Consequently, in order to process separate bytes in ARM, one have to use 32-bit registers anyway. So, LDRSB loads symbol from string into R0, one by one. Next CMP and BEQ instructions checks, if loaded symbol is 0. If not 0, control passing to loop body begin. And if 0, loop is finishing. At the end of function, a dierence between eos and str is calculated, 1 is also subtracting, and resulting value is returned via R0. N.B. Registers was not saved in this function. That’s because by ARM calling convention, R0-R3 registers are “scratch registers”, they are intended for arguments passing, its values may not be restored upon function exit since calling function will not use them anymore. Consequently, they may be used for anything we want. Other registers are not used here, so that is why we have nothing to save on the stack. Thus, control may be returned back to calling function by simple jump (BX), to address in theLR register. 102 13.2. ARM CHAPTER 13. STRLEN() 13.2.2 Optimizing Xcode (LLVM) + thumb mode Listing 13.3: Optimizing Xcode (LLVM) + thumb mode _strlen MOV R1, R0 loc_2DF6 ; CODE XREF: _strlen+8 LDRB.W R2, [R1],#1 CMP R2, #0 BNE loc_2DF6 MVNS R0, R0 ADD R0, R1 BX LR As optimizing LLVM concludes, space on the stack for eos and str may not be allocated, and these variables may always be stored right in registers. Before loop body beginning, str will always be in R0, and eos—in R1. “LDRB.W R2, [R1],#1” instruction loads byte from memory at the address R1 into R2, sign-extending it to 32-bit value, but not only that. #1 at the instruction’s end calling “Post-indexed addressing”, this means, 1 is to be added to the R1 a er byte load. That’s convenient when accessing arrays. There is no such addressing mode in x86, but it is present in some other processors, even on PDP-11. There is a legend the pre-increment, post-increment, pre-decrement and post-decrement modes in PDP-11, were “guilty” in appearance such C language (which developed on PDP-11) constructs as *ptr++, *++ptr, *ptr--, *--ptr. By the way, this is one of hard to memorize C feature. This is how it is: C term ARM term C statement how it works Post-increment post-indexed addressing *ptr++ use *ptr value, then increment ptr pointer Post-decrement post-indexed addressing *ptr-- use *ptr value, then decrement ptr pointer Pre-increment pre-indexed addressing *++ptr increment ptr pointer, then use *ptr value Pre-decrement post-indexed addressing *--ptr decrement ptr pointer, then use *ptr value Dennis Ritchie (one of C language creators) mentioned that it is, probably, was invented by Ken Thompson (another C creator) because this processor feature was present in PDP-7 [28][29]. Thus, C language compilers may use it, if it is present in target processor. Then one may spot CMP and BNE2 in loop body, these instructions continue operation until 0 will be met in string. MVNS3 (inverting all bits, NOT in x86 analogue) instructions and ADD computes 푒표푠−푠푡푟 −1. In fact, these two instructions computes 푅0 = 푠푡푟 + 푒표푠, which is eectively equivalent to what was in source code, and why it is so, I already described here (13.1.5). Apparently, LLVM, just like GCC, concludes this code will be shorter, or faster. 13.2.3 Optimizing Keil + ARM mode Listing 13.4: Optimizing Keil + ARM mode _strlen MOV R1, R0 loc_2C8 ; CODE XREF: _strlen+14 LDRB R2, [R1],#1 CMP R2, #0 SUBEQ R0, R1, R0 SUBEQ R0, R0, #1 BNE loc_2C8 BX LR 2(PowerPC, ARM) Branch if Not Equal 3MoVe Not 103 13.2. ARM CHAPTER 13. STRLEN() Almost the same what we saw before, with the exception the푠푡푟−푒표푠−1expression may be computed not at the function’s end, but right in loop body. -EQsuix, as we may recall, means the instruction will be executed only if operands in executed before CMP were equal to each other. Thus, if 0 will be in the R0 register, both SUBEQ instructions are to be executed and result is leaving in the R0 register. 104 CHAPTER 14. DIVISION BY 9 Chapter 14 Division by 9 Very simple function: int f(int a) { return a/9; }; 14.1 x86 ...is compiled in a very predictable way: Listing 14.1: MSVC _a$ = 8 ; size = 4 _f PROC push ebp mov ebp, esp mov eax, DWORD PTR _a$[ebp] cdq ; sign extend EAX to EDX:EAX mov ecx, 9 idiv ecx pop ebp ret 0 _f ENDP IDIV divides 64-bit number stored in the EDX:EAX register pair by value in the ECX register. As a result, EAX will contain quotient1, and EDX —remainder. Result is returning from the f() function in the EAX register, so, the value is not moved anymore a er division operation, it is in right place already. Since IDIV requires value in the EDX:EAX register pair, CDQ instruction (before IDIV) extending value in the EAX to 64-bit value taking value sign into account, just as MOVSX (13.1.1) does. If we turn optimization on (/Ox), we got: Listing 14.2: Optimizing MSVC _a$ = 8 ; size = 4 _f PROC mov ecx, DWORD PTR _a$[esp-4] mov eax, 954437177 ; 38e38e39H imul ecx sar edx, 1 mov eax, edx shr eax, 31 ; 0000001fH add eax, edx ret 0 _f ENDP 1result of division 105 14.2. ARM CHAPTER 14. DIVISION BY 9 This is —division by multiplication. Multiplication operation works much faster. And it is possible to use the trick 2 to produce a code which is eectively equivalent and faster. This is also called “strength reduction” in compiler optimization. GCC 4.4.1 even without optimization turned on, generates almost the same code as MSVC with optimization turned on: Listing 14.3: Non-optimizing GCC 4.4.1 public f f proc near arg_0 = dword ptr 8 push ebp mov ebp, esp mov ecx, [ebp+arg_0] mov edx, 954437177 ; 38E38E39h mov eax, ecx imul edx sar edx, 1 mov eax, ecx sar eax, 1Fh mov ecx, edx sub ecx, eax mov eax, ecx pop ebp retn f endp 14.2 ARM ARM processor, just like in any other ”pure” RISC-processors, lacks division instruction It lacks also a single instruction for multiplication by 32-bit constant. By taking advantage of the one clever trick (or hack), it is possible to do division using only three instructions: addition, subtraction and bit shi s (17). Here is an example of 32-bit number division by 10 from [20, 3.3 Division by a Constant]. Quotient and remainder on output. ; takes argument in a1 ; returns quotient in a1, remainder in a2 ; cycles could be saved if only divide or remainder is required SUB a2, a1, #10 ; keep (x-10) for later SUB a1, a1, a1, lsr #2 ADD a1, a1, a1, lsr #4 ADD a1, a1, a1, lsr #8 ADD a1, a1, a1, lsr #16 MOV a1, a1, lsr #3 ADD a3, a1, a1, asl #2 SUBS a2, a2, a3, asl #1 ; calc (x-10) - (x/10)*10 ADDPL a1, a1, #1 ; fix-up quotient ADDMI a2, a2, #10 ; fix-up remainder MOV pc, lr 14.2.1 Optimizing Xcode (LLVM) + ARM mode __text:00002C58 39 1E 08 E3 E3 18 43 E3 MOV R1, 0x38E38E39 __text:00002C60 10 F1 50 E7 SMMUL R0, R0, R1 __text:00002C64 C0 10 A0 E1 MOV R1, R0,ASR#1 __text:00002C68 A0 0F 81 E0 ADD R0, R1, R0,LSR#31 __text:00002C6C 1E FF 2F E1 BX LR 2Read more about division by multiplication in [35, 10-3] 106 14.3. HOW IT WORKS CHAPTER 14. DIVISION BY 9 This code is mostly the same to what was generated by optimizing MSVC and GCC. Apparently, LLVM use the same algo- rithm for constants generating. Observant reader may ask, how MOV writes 32-bit value in register, while this is not possible in ARM mode. it is impossible indeed, but, as we see, there are 8 bytes per instruction instead of standard 4, in fact, there are two instructions. First instruc- tion loading 0x8E39 value into low 16 bit of register and second instruction is in fact MOVT, it loading 0x383E into high 16-bit of register. IDA is aware of such sequences, and for the sake of compactness, reduced it to one single “pseudo-instruction”. SMMUL (Signed Most Significant Word Multiply) instruction multiply numbers treating them as signed numbers, and leaving high 32-bit part of result in the R0 register, dropping low 32-bit part of result. “MOV R1, R0,ASR#1” instruction is arithmetic shi right by one bit. “ADD R0, R1, R0,LSR#31” is 푅0 = 푅1 + 푅0 >> 31 As a matter of fact, there is no separate shi ing instruction in ARM mode. Instead, an instructions like (MOV,ADD,SUB,RSB)3 may be supplied by option, is the second operand must be shi ed, if yes, by what value and how. ASR meaning Arithmetic Shi Right, LSR—Logican Shi Right. 14.2.2 Optimizing Xcode (LLVM) + thumb-2 mode MOV R1, 0x38E38E39 SMMUL.W R0, R0, R1 ASRS R1, R0, #1 ADD.W R0, R1, R0,LSR#31 BX LR There are separate instructions for shi ing in thumb mode, and one of them is used here—ASRS (arithmetic shi right). 14.2.3 Non-optimizing Xcode (LLVM) and Keil Non-optimizing LLVM does not generate code we saw before in this section, but inserts a call to library function ___divsi3 instead. What about Keil: it inserts call to library function __aeabi_idivmod in all cases. 14.3 How it works That’s how division can be replaced by multiplication and division by 2푛 numbers: 푟푒푠푢푙푡 = 푖푛푝푢푡 푑푖푣푖푠표푟 = 푖푛푝푢푡 ⋅ 2푛 푑푖푣푖푠표푟 2푛 = 푖푛푝푢푡 ⋅ 푀 2푛 Where 푀 is magic-coeicient. That’s how 푀 can be computed: 푀 = 2푛 푑푖푣푖푠표푟 So these code snippets are usually have this form: 푟푒푠푢푙푡 = 푖푛푝푢푡 ⋅ 푀 2푛 푛 can be arbitrary number, it may be 32 (then high part of multiplication result is taked from EDX or RDX register), or 31 (then high part of multiplication result is shi ed right additionally). 푛 is choosen in order to minimize error. When doing signed division, sign of multiplication result also added to the output result. Take a look at the dierence: int f3_32_signed(int a) { return a/3; }; unsigned int f3_32_unsigned(unsigned int a) { 3These instructions are also called “data processing instructions” 107 14.4. GETTING DIVISOR CHAPTER 14. DIVISION BY 9 return a/3; }; In the unsigned version of function, magic-coeicient is 0xAAAAAAAB and multiplication result is divided by 233. In the signed version of function, magic-coeicient is 0x55555556 and multiplication result is divided by 232. Sign also taken from multiplication result: high 32 bits of result is shi ed by 31 (leaving sign in least significant bit of EAX). 1 is added to the final result if sign is negative. Listing 14.4: MSVC 2012 /Ox _f3_32_unsigned PROC mov eax, -1431655765 ; aaaaaaabH mul DWORD PTR _a$[esp-4] ; unsigned multiply shr edx, 1 mov eax, edx ret 0 _f3_32_unsigned ENDP _f3_32_signed PROC mov eax, 1431655766 ; 55555556H imul DWORD PTR _a$[esp-4] ; signed multiply mov eax, edx shr eax, 31 ; 0000001fH add eax, edx ; add 1 if sign is negative ret 0 _f3_32_signed ENDP Read more about it in [35, 10-3]. 14.4 Getting divisor 14.4.1 Variant #1 O en, the code has a form of: mov eax, MAGICAL CONSTANT imul input value sar edx, SHIFTING COEFFICIENT ; signed division by 2^x using arithmetic shift right mov eax, edx shr eax, 31 add eax, edx Let’s denote 32-bit magic-coeicient as 푀, shi ing coeicient by 퐶 and divisor by 퐷. The divisor we need to get is: 퐷 = 232+퐶 푀 For example: Listing 14.5: Optimizing MSVC 2012 mov eax, 2021161081 ; 78787879H imul DWORD PTR _a$[esp-4] sar edx, 3 mov eax, edx shr eax, 31 ; 0000001fH add eax, edx This is: 퐷 = 232+3 2021161081 Numbers are larger than 32-bit ones, so I use Wolfram Mathematica for convenience: 108 14.4. GETTING DIVISOR CHAPTER 14. DIVISION BY 9 Listing 14.6: Wolfram Mathematica In[1]:=N[2^(32+3)/2021161081] Out[1]:=17. So the divisor from the code I used for example is 17. As of x64 division, things are the same, but 264 should be used instead of 232: uint64_t f1234(uint64_t a) { return a/1234; }; Listing 14.7: MSVC 2012 x64 /Ox f1234 PROC mov rax, 7653754429286296943 ; 6a37991a23aead6fH mul rcx shr rdx, 9 mov rax, rdx ret 0 f1234 ENDP Listing 14.8: Wolfram Mathematica In[1]:=N[2^(64+9)/16^^6a37991a23aead6f] Out[1]:=1234. 14.4.2 Variant #2 A variant with omitted arithmetic shi is also exist: mov eax, 55555556h ; 1431655766 imul ecx mov eax, edx shr eax, 1Fh The method of getting divisor is simplified: 퐷 = 232 푀 As of my example, this is: 퐷 = 232 1431655766 And again I use Wolfram Mathematica: Listing 14.9: Wolfram Mathematica In[1]:=N[2^32/16^^55555556] Out[1]:=3. The divisor is 3. 109 CHAPTER 15. WORKING WITH FPU Chapter 15 Working with FPU FPU1—is a device within main CPU specially designed to deal with floating point numbers. It was called coprocessor in past. It stay aside of the main CPU and looks like programmable calculator in some way and. It is worth to study stack machines2 before FPU studying, or learn Forth language basics3. It is interesting to know that in past (before 80486 CPU) coprocessor was a separate chip and it was not always settled on motherboard. It was possible to buy it separately and install 4. Starting at 80486 DX CPU, FPU is always present in it. FWAIT instruction may remind us that fact—it switches CPU to waiting state, so it can wait until FPU finishes its work. An- other rudiment is the fact that FPU-instruction opcodes are started with so called “escape”-opcodes (D8..DF), i.e., opcodes passed into FPU. FPU has a stack capable to hold 8 80-bit registers, each register can hold a number in IEEE 7545format. C/C++ language oer at least two floating number types, float (single-precision6, 32 bits) 7 and double (double-precision8, 64 bits). GCC also supports long double type (extended precision9, 80 bit) but MSVC is not. float type requires the same number of bits as int type in 32-bit environment, but number representation is completely dif- ferent. Number consisting of sign, significand (also called fraction) and exponent. Function having float or double among argument list is getting the value via stack. If function returns float or double value, it leaves the value in the ST(0) register —at top of FPU stack. 15.1 Simple example Let’s consider simple example: double f (double a, double b) { return a/3.14 + b*4.1; 1Floating-point unit 2http://en.wikipedia.org/wiki/Stack_machine 3http://en.wikipedia.org/wiki/Forth_(programming_language) 4For example, John Carmack used fixed-point arithmetic values in his Doom video game, stored in 32-bit GPR registers (16 bit for intergral part and another 16 bit for fractional part), so the Doom could work on 32-bit computer without FPU, i.e., 80386 and 80486 SX 5http://en.wikipedia.org/wiki/IEEE_754-2008 6http://en.wikipedia.org/wiki/Single-precision_floating-point_format 7single precision float numbers format is also addressed in the Working with the float type as with a structure (18.6.2) section 8http://en.wikipedia.org/wiki/Double-precision_floating-point_format 9http://en.wikipedia.org/wiki/Extended_precision 110 15.1. SIMPLE EXAMPLE CHAPTER 15. WORKING WITH FPU }; 15.1.1 x86 Compile it in MSVC 2010: Listing 15.1: MSVC 2010 CONST SEGMENT __real@4010666666666666 DQ 04010666666666666r ; 4.1 CONST ENDS CONST SEGMENT __real@40091eb851eb851f DQ 040091eb851eb851fr ; 3.14 CONST ENDS _TEXT SEGMENT _a$ = 8 ; size = 8 _b$ = 16 ; size = 8 _f PROC push ebp mov ebp, esp fld QWORD PTR _a$[ebp] ; current stack state: ST(0) = _a fdiv QWORD PTR __real@40091eb851eb851f ; current stack state: ST(0) = result of _a divided by 3.13 fld QWORD PTR _b$[ebp] ; current stack state: ST(0) = _b; ST(1) = result of _a divided by 3.13 fmul QWORD PTR __real@4010666666666666 ; current stack state: ST(0) = result of _b * 4.1; ST(1) = result of _a divided by 3.13 faddp ST(1), ST(0) ; current stack state: ST(0) = result of addition pop ebp ret 0 _f ENDP FLD takes 8 bytes from stack and load the number into the ST(0) register, automatically converting it into internal 80-bit format extended precision). FDIV divides value in the ST(0) register by number storing at address __real@40091eb851eb851f —3.14 value is coded there. Assembler syntax missing floating point numbers, so, what we see here is hexadecimal representation of 3.14 number in 64-bit IEEE 754 encoded. A er FDIV execution, ST(0) will hold quotient10. By the way, there is also FDIVP instruction, which divides ST(1) by ST(0), popping both these values from stack and then pushing result. If you know Forth language11, you will quickly understand that this is stack machine12. Next FLD instruction pushing b value into stack. A er that, quotient is placed to the ST(1) register, and the ST(0) will hold b value. Next FMUL instruction do multiplication: b from the ST(0) register by value at __real@4010666666666666 (4.1 number is there) and leaves result in the ST(0) register. Very last FADDP instruction adds two values at top of stack, storing result to the ST(1) register and then popping value at ST(1), hereby leaving result at top of stack in the ST(0). 10result of division 11http://en.wikipedia.org/wiki/Forth_(programming_language) 12http://en.wikipedia.org/wiki/Stack_machine 111 15.1. SIMPLE EXAMPLE CHAPTER 15. WORKING WITH FPU The function must return result in the ST(0) register, so, a er FADDP there are no any other instructions except of function epilogue. GCC 4.4.1 (with -O3 option) emits the same code, however, slightly dierent: Listing 15.2: Optimizing GCC 4.4.1 public f f proc near arg_0 = qword ptr 8 arg_8 = qword ptr 10h push ebp fld ds:dbl_8048608 ; 3.14 ; stack state now: ST(0) = 3.13 mov ebp, esp fdivr [ebp+arg_0] ; stack state now: ST(0) = result of division fld ds:dbl_8048610 ; 4.1 ; stack state now: ST(0) = 4.1, ST(1) = result of division fmul [ebp+arg_8] ; stack state now: ST(0) = result of multiplication, ST(1) = result of division pop ebp faddp st(1), st ; stack state now: ST(0) = result of addition retn f endp The dierence is that, first of all, 3.14 is pushed to stack (into ST(0)), and then value in arg_0 is divided by value in the ST(0) register. FDIVR meaning Reverse Divide —to divide with divisor and dividend swapped with each other. There is no likewise in- struction for multiplication since multiplication is commutative operation, so we have just FMUL without its -R counterpart. FADDP adding two values but also popping one value from stack. A er that operation, ST(0) holds the sum. This fragment of disassembled code was produced using IDA which named the ST(0) register as ST for short. 15.1.2 ARM: Optimizing Xcode (LLVM) + ARM mode Until ARM has floating standardized point support, several processor manufacturers may add their own instructions exten- sions. Then, VFP (Vector Floating Point) was standardized. One important dierence from x86, there you working with FPU-stack, but here, in ARM, there are no any stack, you work just with registers. f VLDR D16, =3.14 VMOV D17, R0, R1 ; load a VMOV D18, R2, R3 ; load b VDIV.F64 D16, D17, D16 ; a/3.14 VLDR D17, =4.1 VMUL.F64 D17, D18, D17 ; b*4.1 VADD.F64 D16, D17, D16 ; + VMOV R0, R1, D16 BX LR 112 15.1. SIMPLE EXAMPLE CHAPTER 15. WORKING WITH FPU dbl_2C98 DCFD 3.14 ; DATA XREF: f dbl_2CA0 DCFD 4.1 ; DATA XREF: f+10 So, we see here new registers used, with D prefix. These are 64-bit registers, there are 32 of them, and these can be used both for floating-point numbers (double) but also for SIMD (it is called NEON here in ARM). There are also 32 32-bit S-registers, they are intended to be used for single precision floating pointer numbers (float). It is easy to remember: D-registers are intended for double precision numbers, while S-registers —for single precision numbers. Both (3.14 and 4.1) constants are stored in memory in IEEE 754 form. VLDR and VMOV instructions, as it can be easily deduced, are analogous to the LDR and MOV instructions, but they works with D-registers. It should be noted that these instructions, just like D-registers, are intended not only for floating point numbers, but can be also used for SIMD (NEON) operations and this will also be revealed soon. Arguments are passed to function in common way, via R-registers, however, each number having double precision has size 64-bits, so, for passing each, two R-registers are needed. “VMOV D17, R0, R1” at the very beginning, composing two 32-bit values from R0 and R1 into one 64-bit value and saves it to D17. “VMOV R0, R1, D16” is inverse operation, what was in D16 leaving in two R0 and R1 registers, since double-precision number, needing 64 bits for storage, is returning in the R0 and R1 registers pair. VDIV, VMUL and VADD, are instruction for floating point numbers processing, computing, quotient13, product14and sum15, respectively. The code for thumb-2 is same. 15.1.3 ARM: Optimizing Keil + thumb mode f PUSH {R3-R7,LR} MOVS R7, R2 MOVS R4, R3 MOVS R5, R0 MOVS R6, R1 LDR R2, =0x66666666 LDR R3, =0x40106666 MOVS R0, R7 MOVS R1, R4 BL __aeabi_dmul MOVS R7, R0 MOVS R4, R1 LDR R2, =0x51EB851F LDR R3, =0x40091EB8 MOVS R0, R5 MOVS R1, R6 BL __aeabi_ddiv MOVS R2, R7 MOVS R3, R4 BL __aeabi_dadd POP {R3-R7,PC} dword_364 DCD 0x66666666 ; DATA XREF: f+A dword_368 DCD 0x40106666 ; DATA XREF: f+C dword_36C DCD 0x51EB851F ; DATA XREF: f+1A dword_370 DCD 0x40091EB8 ; DATA XREF: f+1C Keil generates for processors not supporting FPU or NEON. So, double-precision floating numbers are passed via generic R-registers, and instead of FPU-instructions, service library functions are called (like__aeabi_dmul,__aeabi_ddiv,__aeabi_dadd ) which emulates multiplication, division and addition floating-point numbers. Of course, that is slower than FPU-coprocessor, but it is better than nothing. By the way, similar FPU-emulating libraries were very popular in x86 world when coprocessors were rare and expensive, and were installed only on expensive computers. 13result of division 14result of multiplication 15result of addition 113 15.2. PASSING FLOATING POINT NUMBER VIA ARGUMENTS CHAPTER 15. WORKING WITH FPU FPU-coprocessor emulating calledso float orarmelin ARM world, while using coprocessor’s FPU-instructions calledhard float or armhf. For example, Linux kernel for Raspberry Pi is compiled in two variants. In so float case, arguments will be passed via R-registers, and in hard float case —via D-registers. And that is what do not let you use e.g. armhf-libraries from armel-code or vice versa, so that is why all code in Linux distribution must be compiled according to the chosen calling convention. 15.2 Passing floating point number via arguments #include #include int main () { printf ("32.01 ^ 1.54 = %lf\n", pow (32.01,1.54)); return 0; } 15.2.1 x86 Let’s see what we got in (MSVC 2010): Listing 15.3: MSVC 2010 CONST SEGMENT __real@40400147ae147ae1 DQ 040400147ae147ae1r ; 32.01 __real@3ff8a3d70a3d70a4 DQ 03ff8a3d70a3d70a4r ; 1.54 CONST ENDS _main PROC push ebp mov ebp, esp sub esp, 8 ; allocate place for the first variable fld QWORD PTR __real@3ff8a3d70a3d70a4 fstp QWORD PTR [esp] sub esp, 8 ; allocate place for the second variable fld QWORD PTR __real@40400147ae147ae1 fstp QWORD PTR [esp] call _pow add esp, 8 ; "return back" place of one variable. ; in local stack here 8 bytes still reserved for us. ; result now in ST(0) fstp QWORD PTR [esp] ; move result from ST(0) to local stack for printf() push OFFSET $SG2651 call _printf add esp, 12 xor eax, eax pop ebp ret 0 _main ENDP FLD and FSTP are moving variables from/to data segment to FPU stack. pow()16 taking both values from FPU-stack and returns result in the ST(0) register. printf() takes 8 bytes from local stack and interpret them as double type variable. 16standard C function, raises a number to the given power 114 15.2. PASSING FLOATING POINT NUMBER VIA ARGUMENTS CHAPTER 15. WORKING WITH FPU 15.2.2 ARM + Non-optimizing Xcode (LLVM) + thumb-2 mode _main var_C = -0xC PUSH {R7,LR} MOV R7, SP SUB SP, SP, #4 VLDR D16, =32.01 VMOV R0, R1, D16 VLDR D16, =1.54 VMOV R2, R3, D16 BLX _pow VMOV D16, R0, R1 MOV R0, 0xFC1 ; "32.01 ^ 1.54 = %lf\n" ADD R0, PC VMOV R1, R2, D16 BLX _printf MOVS R1, 0 STR R0, [SP,#0xC+var_C] MOV R0, R1 ADD SP, SP, #4 POP {R7,PC} dbl_2F90 DCFD 32.01 ; DATA XREF: _main+6 dbl_2F98 DCFD 1.54 ; DATA XREF: _main+E As I wrote before, 64-bit floating pointer numbers passing in R-registers pairs. This is code is redundant for a little (certainly because optimization is turned o), because, it is actually possible to load values into R-registers straightforwardly without touching D-registers. So, as we see, _pow function receiving first argument in R0 and R1, and the second one in R2 and R3. Function leaves result in R0 and R1. Result of _pow is moved into D16, then in R1 and R2 pair, from where printf() will take this number. 15.2.3 ARM + Non-optimizing Keil + ARM mode _main STMFD SP!, {R4-R6,LR} LDR R2, =0xA3D70A4 ; y LDR R3, =0x3FF8A3D7 LDR R0, =0xAE147AE1 ; x LDR R1, =0x40400147 BL pow MOV R4, R0 MOV R2, R4 MOV R3, R1 ADR R0, a32_011_54Lf ; "32.01 ^ 1.54 = %lf\n" BL __2printf MOV R0, #0 LDMFD SP!, {R4-R6,PC} y DCD 0xA3D70A4 ; DATA XREF: _main+4 dword_520 DCD 0x3FF8A3D7 ; DATA XREF: _main+8 ; double x x DCD 0xAE147AE1 ; DATA XREF: _main+C dword_528 DCD 0x40400147 ; DATA XREF: _main+10 a32_011_54Lf DCB "32.01 ^ 1.54 = %lf",0xA,0 ; DATA XREF: _main+24 D-registers are not used here, only R-register pairs are used. 115 15.3. COMPARISON EXAMPLE CHAPTER 15. WORKING WITH FPU 15.3 Comparison example Let’s try this: double d_max (double a, double b) { if (a>b) return a; return b; }; 15.3.1 x86 Despite simplicity of the function, it will be harder to understand how it works. MSVC 2010 generated: Listing 15.4: MSVC 2010 PUBLIC _d_max _TEXT SEGMENT _a$ = 8 ; size = 8 _b$ = 16 ; size = 8 _d_max PROC push ebp mov ebp, esp fld QWORD PTR _b$[ebp] ; current stack state: ST(0) = _b ; compare _b (ST(0)) and _a, and pop register fcomp QWORD PTR _a$[ebp] ; stack is empty here fnstsw ax test ah, 5 jp SHORT $LN1@d_max ; we are here only if a>b fld QWORD PTR _a$[ebp] jmp SHORT $LN2@d_max $LN1@d_max: fld QWORD PTR _b$[ebp] $LN2@d_max: pop ebp ret 0 _d_max ENDP So, FLD loading _b into the ST(0) register. FCOMP compares the value in the ST(0) register with what is in _a value and set C3/C2/C0 bits in FPU status word register. This is 16-bit register reflecting current state of FPU. For now C3/C2/C0 bits are set, but unfortunately, CPU before Intel P6 17 has not any conditional jumps instructions which are checking these bits. Probably, it is a matter of history (remember: FPU was separate chip in past). Modern CPU starting at Intel P6 has FCOMI/FCOMIP/FUCOMI/FUCOMIP instructions —which does the same, but modifies CPU flags ZF/PF/CF. A er bits are set, the FCOMP instruction popping one variable from stack. This is what distinguish it from FCOM, which is just comparing values, leaving the stack at the same state. FNSTSW copies FPU status word register to the AX. Bits C3/C2/C0 are placed at positions 14/10/8, they will be at the same positions in the AX register and all they are placed in high part of the AX —AH. 17Intel P6 is Pentium Pro, Pentium II, etc 116 15.3. COMPARISON EXAMPLE CHAPTER 15. WORKING WITH FPU • If b>a in our example, then C3/C2/C0 bits will be set as following: 0, 0, 0. • If a>b, then bits will be set: 0, 0, 1. • If a=b, then bits will be set: 1, 0, 0. A er test ah, 5 execution, bits C3 and C1 will be set to 0, but at positions 0 and 2 (in the AH registers) C0 and C2 bits will be leaved. Now let’s talk about parity flag. Another notable epoch rudiment: One common reason to test the parity flag actually has nothing to do with parity. The FPU has four condition flags (C0 to C3), but they can not be tested directly, and must instead be first copied to the flags register. When this happens, C0 is placed in the carry flag, C2 in the parity flag and C3 in the zero flag. The C2 flag is set when e.g. incomparable floating point values (NaN or unsupported format) are compared with the FUCOM instructions.18 This flag is to be set to 1 if ones number is even. And to 0 if odd. Thus, PF flag will be set to 1 if both C0 and C2 are set to 0 or both are 1. And then following JP (jump if PF==1) will be trig- gered. If we recall values of the C3/C2/C0 for various cases, we will see the conditional jump JP will be triggered in two cases: if b>a or a==b (C3 bit is already not considering here since it was cleared while execution of the test ah, 5 instruction). It is all simple therea er. If conditional jump was triggered, FLD will load the _b value to the ST(0) register, and if it is not triggered, the value of the _a variable will be loaded. But it is not over yet! 15.3.2 Now let’s compile it with MSVC 2010 with optimization option /Ox Listing 15.5: Optimizing MSVC 2010 _a$ = 8 ; size = 8 _b$ = 16 ; size = 8 _d_max PROC fld QWORD PTR _b$[esp-4] fld QWORD PTR _a$[esp-4] ; current stack state: ST(0) = _a, ST(1) = _b fcom ST(1) ; compare _a and ST(1) = (_b) fnstsw ax test ah, 65 ; 00000041H jne SHORT $LN5@d_max fstp ST(1) ; copy ST(0) to ST(1) and pop register, leave (_a) on top ; current stack state: ST(0) = _a ret 0 $LN5@d_max: fstp ST(0) ; copy ST(0) to ST(0) and pop register, leave (_b) on top ; current stack state: ST(0) = _b ret 0 _d_max ENDP FCOMis distinguished fromFCOMPin that sense that it just comparing values and leaves FPU stack in the same state. Unlike previous example, operands here in reversed order. And that is why result of comparison in the C3/C2/C0 will be dierent: • If a>b in our example, then C3/C2/C0 bits will be set as: 0, 0, 0. • If b>a, then bits will be set as: 0, 0, 1. • If a=b, then bits will be set as: 1, 0, 0. 117 15.3. COMPARISON EXAMPLE CHAPTER 15. WORKING WITH FPU It can be said, test ah, 65 instruction just leaves two bits —C3 and C0. Both will be zeroes if a>b: in that case JNE jump will not be triggered. Then FSTP ST(1) is following —this instruction copies value in the ST(0) into operand and popping one value from FPU stack. In other words, the instruction copies ST(0) (where _a value is now) into the ST(1). A er that, two values of the _a are at the top of stack now. A er that, one value is popping. A er that, ST(0) will contain _a and function is finished. Conditional jump JNE is triggered in two cases: of b>a or a==b. ST(0) into ST(0) will be copied, it is just like idle (NOP) operation, then one value is popping from stack and top of stack (ST(0)) will contain what was in the ST(1) before (that is _b). Then function finishes. The instruction used here probably since FPU has no instruction to pop value from stack and not to store it anywhere. Well, but it is still not over. 15.3.3 GCC 4.4.1 Listing 15.6: GCC 4.4.1 d_max proc near b = qword ptr -10h a = qword ptr -8 a_first_half = dword ptr 8 a_second_half = dword ptr 0Ch b_first_half = dword ptr 10h b_second_half = dword ptr 14h push ebp mov ebp, esp sub esp, 10h ; put a and b to local stack: mov eax, [ebp+a_first_half] mov dword ptr [ebp+a], eax mov eax, [ebp+a_second_half] mov dword ptr [ebp+a+4], eax mov eax, [ebp+b_first_half] mov dword ptr [ebp+b], eax mov eax, [ebp+b_second_half] mov dword ptr [ebp+b+4], eax ; load a and b to FPU stack: fld [ebp+a] fld [ebp+b] ; current stack state: ST(0) - b; ST(1) - a fxch st(1) ; this instruction swapping ST(1) and ST(0) ; current stack state: ST(0) - a; ST(1) - b fucompp ; compare a and b and pop two values from stack, i.e., a and b fnstsw ax ; store FPU status to AX sahf ; load SF, ZF, AF, PF, and CF flags state from AH setnbe al ; store 1 to AL if CF=0 and ZF=0 test al, al ; AL==0 ? jz short loc_8048453 ; yes fld [ebp+a] jmp short locret_8048456 loc_8048453: fld [ebp+b] 118 15.3. COMPARISON EXAMPLE CHAPTER 15. WORKING WITH FPU locret_8048456: leave retn d_max endp FUCOMPP —is almost like FCOM, but popping both values from stack and handling “not-a-numbers” dierently. More about not-a-numbers: FPU is able to deal with a special values which are not-a-numbers or NaNs19. These are infinity, result of dividing by 0, etc. Not-a-numbers can be “quiet” and “signaling”. It is possible to continue to work with “quiet” NaNs, but if one try to do any operation with “signaling” NaNs —an exception will be raised. FCOM will raise exception if any operand —NaN. FUCOM will raise exception only if any operand —signaling NaN (SNaN). The following instruction is SAHF —this is rare instruction in the code which is not use FPU. 8 bits from AH is movinto into lower 8 bits of CPU flags in the following order: SF:ZF:-:AF:-:PF:-:CF <- AH. Let’s remember the FNSTSW is moving interesting for us bits C3/C2/C0 into the AH and they will be in positions 6, 2, 0 in the AH register. In other words, fnstsw ax / sahf instruction pair is moving C3/C2/C0 into ZF, PF, CF CPU flags. Now let’s also recall, what values of the C3/C2/C0 bits will be set: • If a is greater than b in our example, then C3/C2/C0 bits will be set as: 0, 0, 0. • if a is less than b, then bits will be set as: 0, 0, 1. • If a=b, then bits will be set: 1, 0, 0. In other words, a er FUCOMPP/FNSTSW/SAHF instructions, we will have these CPU flags states: • If a>b, CPU flags will be set as: ZF=0, PF=0, CF=0. • If ab. Then one will be stored to the AL and the following JZ will not be triggered and function will return _a. In all other cases, _b will be returned. But it is still not over. 15.3.4 GCC 4.4.1 with -O3 optimization turned on Listing 15.7: Optimizing GCC 4.4.1 public d_max d_max proc near arg_0 = qword ptr 8 arg_8 = qword ptr 10h push ebp mov ebp, esp fld [ebp+arg_0] ; _a fld [ebp+arg_8] ; _b ; stack state now: ST(0) = _b, ST(1) = _a fxch st(1) ; stack state now: ST(0) = _a, ST(1) = _b fucom st(1) ; compare _a and _b 19http://en.wikipedia.org/wiki/NaN 20cc is condition code 119 15.3. COMPARISON EXAMPLE CHAPTER 15. WORKING WITH FPU fnstsw ax sahf ja short loc_8048448 ; store ST(0) to ST(0) (idle operation), pop value at top of stack, leave _b at top fstp st jmp short loc_804844A loc_8048448: ; store _a to ST(0), pop value at top of stack, leave _a at top fstp st(1) loc_804844A: pop ebp retn d_max endp It is almost the same except one: JA usage instead of SAHF. Actually, conditional jump instructions checking “larger”, “lesser” or “equal” for unsigned number comparison (JA, JAE, JBE, JBE, JE/JZ, JNA, JNAE, JNB, JNBE, JNE/JNZ) are checking only CF and ZF flags. And C3/C2/C0 bits a er comparison are moving into these flags exactly in the same fashion so condi- tional jumps will work here. JA will work if both CF are ZF zero. Thereby, conditional jumps instructions listed here can be used a er FNSTSW/SAHF instructions pair. It seems, FPU C3/C2/C0 status bits was placed there intentionally so to map them to base CPU flags without additional permutations. 15.3.5 ARM + Optimizing Xcode (LLVM) + ARM mode Listing 15.8: Optimizing Xcode (LLVM) + ARM mode VMOV D16, R2, R3 ; b VMOV D17, R0, R1 ; a VCMPE.F64 D17, D16 VMRS APSR_nzcv, FPSCR VMOVGT.F64 D16, D17 ; copy b to D16 VMOV R0, R1, D16 BX LR A very simple case. Input values are placed into the D17 and D16 registers and then compared with the help of VCMPE instruction. Just like in x86 coprocessor, ARM coprocessor has its own status and flags register, (FPSCR), since there is a need to store coprocessor-specific flags. And just like in x86, there are no conditional jump instruction in ARM, checking bits in coprocessor status register, so there is VMRS instruction, copying 4 bits (N, Z, C, V) from the coprocessor status word into bits of general status (APSR register). VMOVGT is analogue of MOVGT, instruction, to be executed if one operand is greater than other while comparing (GT— Greater Than). If it will be executed, 푏 value will be written into D16, stored at the moment in D17. And if it will not be triggered, then 푎 value will stay in the D16 register. Penultimate instruction VMOV will prepare value in the D16 register for returning via R0 and R1 registers pair. 15.3.6 ARM + Optimizing Xcode (LLVM) + thumb-2 mode Listing 15.9: Optimizing Xcode (LLVM) + thumb-2 mode VMOV D16, R2, R3 ; b VMOV D17, R0, R1 ; a VCMPE.F64 D17, D16 VMRS APSR_nzcv, FPSCR IT GT VMOVGT.F64 D16, D17 VMOV R0, R1, D16 BX LR 120 15.3. COMPARISON EXAMPLE CHAPTER 15. WORKING WITH FPU Almost the same as in previous example, howeverm slightly dierent. As a matter of fact, many instructions in ARM mode can be supplied by condition predicate, and the instruction is to be executed if condition is true. But there is no such thing in thumb mode. There is no place in 16-bit instructions for spare 4 bits where condition can be encoded. However, thumb-2 was extended to make possible to specify predicates to old thumb instructions. Here, is the IDA-generated listing, we see VMOVGT instruction, the same as in previous example. But in fact, usual VMOV is encoded there, but IDA added -GT suix to it, since there is “IT GT” instruction placed right before. IT instruction defines so-called if-then block. A er the instruction, it is possible to place up to 4 instructions, to which predicate suix will be added. In our example, “IT GT” meaning, the next instruction will be executed, if GT(Greater Than) condition is true. Now more complex code fragment, by the way, from “Angry Birds” (for iOS): Listing 15.10: Angry Birds Classic ITE NE VMOVNE R2, R3, D16 VMOVEQ R2, R3, D17 ITEmeaningif-then-elseand it encode suixes for two next instructions. First instruction will execute if condition encoded in ITE (NE, not equal) will be true at the moment, and the second —if the condition will not be true. (Inverse condition of NE is EQ (equal)). Slightly harder, and this fragment from “Angry Birds” as well: Listing 15.11: Angry Birds Classic ITTTT EQ MOVEQ R0, R4 ADDEQ SP, SP, #0x20 POPEQ.W {R8,R10} POPEQ {R4-R7,PC} 4 “T” symbols in instruction mnemonic means the 4 next instructions will be executed if condition is true. That’s why IDA added -EQ suix to each 4 instructions. And if there will be e.g. ITEEE EQ (if-then-else-else-else), then suixes will be set as follows: -EQ -NE -NE -NE Another fragment from “Angry Birds”: Listing 15.12: Angry Birds Classic CMP.W R0, #0xFFFFFFFF ITTE LE SUBLE.W R10, R0, #1 NEGLE R0, R0 MOVGT R10, R0 ITTE (if-then-then-else) means the 1st and 2nd instructions will be executed, if LE (Less or Equal) condition is true, and 3rd—if inverse condition (GT—Greater Than) is true. Compilers usually are not generating all possible combinations. For example, it mentioned “Angry Birds” game (classic version for iOS) only these cases of IT instruction are used: IT, ITE, ITT, ITTE, ITTT, ITTTT. How I learnt this? In IDA it is possible to produce listing files, so I did it, but I also set in options to show 4 bytes of each opcodes . Then, knowing the high part of 16-bit opcode IT is 0xBF, I did this with grep: cat AngryBirdsClassic.lst | grep " BF" | grep "IT" > results.lst By the way, if to program in ARM assembly language manually for thumb-2 mode, with adding conditional suixes, as- sembler will add IT instructions automatically, with respectable flags, where it is necessary. 121 15.3. COMPARISON EXAMPLE CHAPTER 15. WORKING WITH FPU 15.3.7 ARM + Non-optimizing Xcode (LLVM) + ARM mode Listing 15.13: Non-optimizing Xcode (LLVM) + ARM mode b = -0x20 a = -0x18 val_to_return = -0x10 saved_R7 = -4 STR R7, [SP,#saved_R7]! MOV R7, SP SUB SP, SP, #0x1C BIC SP, SP, #7 VMOV D16, R2, R3 VMOV D17, R0, R1 VSTR D17, [SP,#0x20+a] VSTR D16, [SP,#0x20+b] VLDR D16, [SP,#0x20+a] VLDR D17, [SP,#0x20+b] VCMPE.F64 D16, D17 VMRS APSR_nzcv, FPSCR BLE loc_2E08 VLDR D16, [SP,#0x20+a] VSTR D16, [SP,#0x20+val_to_return] B loc_2E10 loc_2E08 VLDR D16, [SP,#0x20+b] VSTR D16, [SP,#0x20+val_to_return] loc_2E10 VLDR D16, [SP,#0x20+val_to_return] VMOV R0, R1, D16 MOV SP, R7 LDR R7, [SP+0x20+b],#4 BX LR Almost the same we already saw, but too much redundant code because of 푎 and 푏 variables storage in local stack, as well as returning value. 15.3.8 ARM + Optimizing Keil + thumb mode Listing 15.14: Optimizing Keil + thumb mode PUSH {R3-R7,LR} MOVS R4, R2 MOVS R5, R3 MOVS R6, R0 MOVS R7, R1 BL __aeabi_cdrcmple BCS loc_1C0 MOVS R0, R6 MOVS R1, R7 POP {R3-R7,PC} loc_1C0 MOVS R0, R4 MOVS R1, R5 POP {R3-R7,PC} Keil not generates special instruction for float numbers comparing since it cannot rely it will be supported on the target CPU, and it cannot be done by straightforward bitwise comparing. So there is called external library function for comparing: 122 15.4. X64 CHAPTER 15. WORKING WITH FPU __aeabi_cdrcmple. N.B. Comparison result is to be leaved in flags, so the following BCS (Carry set - Greater than or equal) instruction may work without any additional code. 15.4 x64 Read more here24 about how float point numbers are processed in x86-64. 123 CHAPTER 16. ARRAYS Chapter 16 Arrays Array is just a set of variables in memory, always lying next to each other, always has same type 1. 16.1 Simple example #include int main() { int a[20]; int i; for (i=0; i<20; i++) a[i]=i*2; for (i=0; i<20; i++) printf ("a[%d]=%d\n", i, a[i]); return 0; }; 16.1.1 x86 Let’s compile: Listing 16.1: MSVC _TEXT SEGMENT _i$ = -84 ; size = 4 _a$ = -80 ; size = 80 _main PROC push ebp mov ebp, esp sub esp, 84 ; 00000054H mov DWORD PTR _i$[ebp], 0 jmp SHORT $LN6@main $LN5@main: mov eax, DWORD PTR _i$[ebp] add eax, 1 mov DWORD PTR _i$[ebp], eax $LN6@main: cmp DWORD PTR _i$[ebp], 20 ; 00000014H jge SHORT $LN4@main mov ecx, DWORD PTR _i$[ebp] 1AKA2 “homogeneous container” 124 16.1. SIMPLE EXAMPLE CHAPTER 16. ARRAYS shl ecx, 1 mov edx, DWORD PTR _i$[ebp] mov DWORD PTR _a$[ebp+edx*4], ecx jmp SHORT $LN5@main $LN4@main: mov DWORD PTR _i$[ebp], 0 jmp SHORT $LN3@main $LN2@main: mov eax, DWORD PTR _i$[ebp] add eax, 1 mov DWORD PTR _i$[ebp], eax $LN3@main: cmp DWORD PTR _i$[ebp], 20 ; 00000014H jge SHORT $LN1@main mov ecx, DWORD PTR _i$[ebp] mov edx, DWORD PTR _a$[ebp+ecx*4] push edx mov eax, DWORD PTR _i$[ebp] push eax push OFFSET $SG2463 call _printf add esp, 12 ; 0000000cH jmp SHORT $LN2@main $LN1@main: xor eax, eax mov esp, ebp pop ebp ret 0 _main ENDP Nothing very special, just two loops: first is filling loop and second is printing loop. shl ecx, 1 instruction is used for value multiplication by 2 in the ECX, more about below 17.3.1. 80 bytes are allocated on the stack for array, that is 20 elements of 4 bytes. Here is what GCC 4.4.1 does: Listing 16.2: GCC 4.4.1 public main main proc near ; DATA XREF: _start+17 var_70 = dword ptr -70h var_6C = dword ptr -6Ch var_68 = dword ptr -68h i_2 = dword ptr -54h i = dword ptr -4 push ebp mov ebp, esp and esp, 0FFFFFFF0h sub esp, 70h mov [esp+70h+i], 0 ; i=0 jmp short loc_804840A loc_80483F7: mov eax, [esp+70h+i] mov edx, [esp+70h+i] add edx, edx ; edx=i*2 mov [esp+eax*4+70h+i_2], edx add [esp+70h+i], 1 ; i++ loc_804840A: cmp [esp+70h+i], 13h 125 16.1. SIMPLE EXAMPLE CHAPTER 16. ARRAYS jle short loc_80483F7 mov [esp+70h+i], 0 jmp short loc_8048441 loc_804841B: mov eax, [esp+70h+i] mov edx, [esp+eax*4+70h+i_2] mov eax, offset aADD ; "a[%d]=%d\n" mov [esp+70h+var_68], edx mov edx, [esp+70h+i] mov [esp+70h+var_6C], edx mov [esp+70h+var_70], eax call _printf add [esp+70h+i], 1 loc_8048441: cmp [esp+70h+i], 13h jle short loc_804841B mov eax, 0 leave retn main endp By the way, a variable has int* type (the pointer to int) —you can try to pass a pointer to array to another function, but it much correctly to say the pointer to the first array element is passed (addresses of another element’s places are calculated in obvious way). If to index this pointer as a[idx], idx just to be added to the pointer and the element placed there (to which calculated pointer is pointing) returned. An interesting example: string of characters like “string” is array of characters and it has const char* type.Index can be applied to this pointer. And that is why it is possible to write like “string”[i] —this is correct C/C++ expression! 16.1.2 ARM + Non-optimizing Keil + ARM mode EXPORT _main _main STMFD SP!, {R4,LR} SUB SP, SP, #0x50 ; allocate place for 20 int variables ; first loop MOV R4, #0 ; i B loc_4A0 loc_494 MOV R0, R4,LSL#1 ; R0=R4*2 STR R0, [SP,R4,LSL#2] ; store R0 to SP+R4<<2 (same as SP+R4*4) ADD R4, R4, #1 ; i=i+1 loc_4A0 CMP R4, #20 ; i<20? BLT loc_494 ; yes, run loop body again ; second loop MOV R4, #0 ; i B loc_4C4 loc_4B0 LDR R2, [SP,R4,LSL#2] ; (second printf argument) R2=*(SP+R4<<4) (same as *(SP+⤦ Ç R4*4)) MOV R1, R4 ; (first printf argument) R1=i ADR R0, aADD ; "a[%d]=%d\n" BL __2printf ADD R4, R4, #1 ; i=i+1 126 16.1. SIMPLE EXAMPLE CHAPTER 16. ARRAYS loc_4C4 CMP R4, #20 ; i<20? BLT loc_4B0 ; yes, run loop body again MOV R0, #0 ; value to return ADD SP, SP, #0x50 ; deallocate place, allocated for 20 int variables LDMFD SP!, {R4,PC} int type requires 32 bits for storage, or 4 bytes, so for storage of 20 int variables, 80 (0x50) bytes are needed, so that is why “SUB SP, SP, #0x50” instruction in function epilogue allocates exactly this amount of space in local stack. In both first and second loops, 푖 loop iterator will be placed in the R4 register. A number to be written into array, is calculating as 푖 ∗ 2 which is eectively equivalent to shi ing le by one bit, so “MOV R0, R4,LSL#1” instruction do this. “STR R0, [SP,R4,LSL#2]” writes R0 contents into array. Here is how a pointer to array element is to be calculated:SP pointing to array begin, R4 is 푖. So shi 푖 le by 2 bits, that is eectively equivalent to multiplication by 4 (since each array element has size of 4 bytes) and add it to address of array begin. The second loop has inverse “LDR R2, [SP,R4,LSL#2]”, instruction, it loads from array value we need, and the pointer to it is calculated likewise. 16.1.3 ARM + Optimizing Keil + thumb mode _main PUSH {R4,R5,LR} ; allocate place for 20 int variables + one more variable SUB SP, SP, #0x54 ; first loop MOVS R0, #0 ; i MOV R5, SP ; pointer to first array element loc_1CE LSLS R1, R0, #1 ; R1=i<<1 (same as i*2) LSLS R2, R0, #2 ; R2=i<<2 (same as i*4) ADDS R0, R0, #1 ; i=i+1 CMP R0, #20 ; i<20? STR R1, [R5,R2] ; store R1 to *(R5+R2) (same R5+i*4) BLT loc_1CE ; yes, i<20, run loop body again ; second loop MOVS R4, #0 ; i=0 loc_1DC LSLS R0, R4, #2 ; R0=i<<2 (same as i*4) LDR R2, [R5,R0] ; load from *(R5+R0) (same as R5+i*4) MOVS R1, R4 ADR R0, aADD ; "a[%d]=%d\n" BL __2printf ADDS R4, R4, #1 ; i=i+1 CMP R4, #20 ; i<20? BLT loc_1DC ; yes, i<20, run loop body again MOVS R0, #0 ; value to return ; deallocate place, allocated for 20 int variables + one more variable ADD SP, SP, #0x54 POP {R4,R5,PC} Thumb code is very similar. Thumb mode has special instructions for bit shi ing (like LSLS), which calculates value to be written into array and address of each element in array as well. Compiler allocates slightly more space in local stack, however, last 4 bytes are not used. 127 16.2. BUFFER OVERFLOW CHAPTER 16. ARRAYS 16.2 Buer overflow So, array indexing is just array[index]. If you study generated code closely, you’ll probably note missing index bounds check- ing, which could check index, if it is less than 20. What if index will be greater than 20? That’s the one C/C++ feature it is o en blamed for. Here is a code successfully compiling and working: #include int main() { int a[20]; int i; for (i=0; i<20; i++) a[i]=i*2; printf ("a[100]=%d\n", a[100]); return 0; }; Compilation results (MSVC 2010): _TEXT SEGMENT _i$ = -84 ; size = 4 _a$ = -80 ; size = 80 _main PROC push ebp mov ebp, esp sub esp, 84 ; 00000054H mov DWORD PTR _i$[ebp], 0 jmp SHORT $LN3@main $LN2@main: mov eax, DWORD PTR _i$[ebp] add eax, 1 mov DWORD PTR _i$[ebp], eax $LN3@main: cmp DWORD PTR _i$[ebp], 20 ; 00000014H jge SHORT $LN1@main mov ecx, DWORD PTR _i$[ebp] shl ecx, 1 mov edx, DWORD PTR _i$[ebp] mov DWORD PTR _a$[ebp+edx*4], ecx jmp SHORT $LN2@main $LN1@main: mov eax, DWORD PTR _a$[ebp+400] push eax push OFFSET $SG2460 call _printf add esp, 8 xor eax, eax mov esp, ebp pop ebp ret 0 _main ENDP I’m running it, and I got: a[100]=760826203 It is just something, occasionally lying in the stack near to array, 400 bytes from its first element. 128 16.2. BUFFER OVERFLOW CHAPTER 16. ARRAYS Indeed, how it could be done dierently? Compiler may generate some additional code for checking index value to be always in array’s bound (like in higher-level programming languages3) but this makes running code slower. OK, we read some values from the stack illegally but what if we could write something to it? Here is what we will write: #include int main() { int a[20]; int i; for (i=0; i<30; i++) a[i]=i; return 0; }; And what we’ve got: _TEXT SEGMENT _i$ = -84 ; size = 4 _a$ = -80 ; size = 80 _main PROC push ebp mov ebp, esp sub esp, 84 ; 00000054H mov DWORD PTR _i$[ebp], 0 jmp SHORT $LN3@main $LN2@main: mov eax, DWORD PTR _i$[ebp] add eax, 1 mov DWORD PTR _i$[ebp], eax $LN3@main: cmp DWORD PTR _i$[ebp], 30 ; 0000001eH jge SHORT $LN1@main mov ecx, DWORD PTR _i$[ebp] mov edx, DWORD PTR _i$[ebp] ; that instruction is obviously redundant mov DWORD PTR _a$[ebp+ecx*4], edx ; ECX could be used as second operand here instead jmp SHORT $LN2@main $LN1@main: xor eax, eax mov esp, ebp pop ebp ret 0 _main ENDP Run compiled program and its crashing. No wonder. Let’s see, where exactly it is crashing. I’m not using debugger anymore since I tried to run it each time, move mouse, etc, when I need just to spot a register’s state at the specific point. That’s why I wrote very minimalistic tool for myself, tracer, which is enough for my tasks. I can also use it just to see, where debuggee is crashed. So let’s see: generic tracer 0.4 (WIN32), http://conus.info/gt New process: C:\PRJ\...\1.exe, PID=7988 EXCEPTION_ACCESS_VIOLATION: 0x15 (), ExceptionInformation⤦ Ç[0]=8 EAX=0x00000000 EBX=0x7EFDE000 ECX=0x0000001D EDX=0x0000001D ESI=0x00000000 EDI=0x00000000 EBP=0x00000014 ESP=0x0018FF48 EIP=0x00000015 FLAGS=PF ZF IF RF PID=7988|Process exit, return code -1073740791 3Java, Python, etc 129 16.2. BUFFER OVERFLOW CHAPTER 16. ARRAYS Now please keep your eyes on registers. Exception occurred at address 0x15. It is not legal address for code —at least for win32 code! We trapped there somehow against our will. It is also interesting fact the EBP register contain 0x14, ECX and EDX —0x1D. Let’s study stack layout more. A er control flow was passed into main(), the value in the EBP register was saved on the stack. Then, 84 bytes was allocated for array and i variable. That’s (20+1)*sizeof(int). The ESP pointing now to the _i variable in the local stack and a er execution of next PUSH something, something will be appeared next to _i. That’s stack layout while control is inside main(): ESP 4 bytes for i ESP+4 80 bytes for a[20] array ESP+84 saved EBP value ESP+88 returning address Instruction a[19]=something writes last int in array bounds (in bounds so far!) Instruction a[20]=something writes something to the place where value from the EBP is saved. Please take a look at registers state at the crash moment. In our case, number 20 was written to 20th element. By the function ending, function epilogue restores original EBP value. (20 in decimal system is 0x14 in hexadecimal). Then, RET instruction was executed, which is eectively equivalent to POP EIP instruction. RET instruction taking returning address from the stack (that is the address inside of CRT), which was called main()), and 21 was stored there (0x15 in hexadecimal). The CPU trapped at the address 0x15, but there is no executable code, so exception was raised. Welcome! It is called buer overflow4. Replace int array by string (char array), create a long string deliberately, and pass it to the program, to the function which is not checking string length and copies it to short buer, and you’ll able to point to a program an address to which it must jump. Not that simple in reality, but that is how it was emerged 5 Let’s try the same code in GCC 4.4.1. We got: public main main proc near a = dword ptr -54h i = dword ptr -4 push ebp mov ebp, esp sub esp, 60h mov [ebp+i], 0 jmp short loc_80483D1 loc_80483C3: mov eax, [ebp+i] mov edx, [ebp+i] mov [ebp+eax*4+a], edx add [ebp+i], 1 loc_80483D1: cmp [ebp+i], 1Dh jle short loc_80483C3 mov eax, 0 leave retn main endp Running this in Linux will produce: Segmentation fault. If we run this in GDB debugger, we getting this: (gdb) r Starting program: /home/dennis/RE/1 Program received signal SIGSEGV, Segmentation fault. 0x00000016 in ?? () 4http://en.wikipedia.org/wiki/Stack_buffer_overflow 5Classic article about it: [22]. 130 16.3. BUFFER OVERFLOW PROTECTION METHODS CHAPTER 16. ARRAYS (gdb) info registers eax 0x0 0 ecx 0xd2f96388 -755407992 edx 0x1d 29 ebx 0x26eff4 2551796 esp 0xbffff4b0 0xbffff4b0 ebp 0x15 0x15 esi 0x0 0 edi 0x0 0 eip 0x16 0x16 eflags 0x10202 [ IF RF ] cs 0x73 115 ss 0x7b 123 ds 0x7b 123 es 0x7b 123 fs 0x0 0 gs 0x33 51 (gdb) Register values are slightly dierent then in win32 example since stack layout is slightly dierent too. 16.3 Buer overflow protection methods There are several methods to protect against it, regardless of C/C++ programmers’ negligence. MSVC has options like6: /RTCs Stack Frame runtime checking /GZ Enable stack checks (/RTCs) One of the methods is to write random value among local variables to stack at function prologue and to check it in function epilogue before function exiting. And if value is not the same, do not execute last instruction RET, but halt (or hang). Process will hang, but that is much better then remote attack to your host. This random value is called “canary” sometimes, it is related to miner’s canary7, they were used by miners in these days, in order to detect poisonous gases quickly. Canaries are very sensetive to mine gases, they become very agitated in case of danger, or even dead. If to compile our very simple array example (16.1) in MSVC with RTC1 and RTCs option, you will see call to@_RTC_CheckStackVars@8 function at the function end, checking “canary” correctness. Let’s see how GCC handles this. Let’s take alloca() (4.2.4) example: #ifdef __GNUC__ #include // GCC #else #include // MSVC #endif #include void f() { char *buf=(char*)alloca (600); #ifdef __GNUC__ snprintf (buf, 600, "hi! %d, %d, %d\n", 1, 2, 3); // GCC #else _snprintf (buf, 600, "hi! %d, %d, %d\n", 1, 2, 3); // MSVC #endif puts (buf); }; By default, without any additional options, GCC 4.7.3 will insert “canary” check into code: 6Wikipedia: compiler-side buer overflow protection methods: http://en.wikipedia.org/wiki/Buffer_overflow_protection 7http://en.wikipedia.org/wiki/Domestic_Canary#Miner.27s_canary 131 16.3. BUFFER OVERFLOW PROTECTION METHODS CHAPTER 16. ARRAYS Listing 16.3: GCC 4.7.3 .LC0: .string "hi! %d, %d, %d\n" f: push ebp mov ebp, esp push ebx sub esp, 676 lea ebx, [esp+39] and ebx, -16 mov DWORD PTR [esp+20], 3 mov DWORD PTR [esp+16], 2 mov DWORD PTR [esp+12], 1 mov DWORD PTR [esp+8], OFFSET FLAT:.LC0 ; "hi! %d, %d, %d\n" mov DWORD PTR [esp+4], 600 mov DWORD PTR [esp], ebx mov eax, DWORD PTR gs:20 ; canary mov DWORD PTR [ebp-12], eax xor eax, eax call _snprintf mov DWORD PTR [esp], ebx call puts mov eax, DWORD PTR [ebp-12] xor eax, DWORD PTR gs:20 ; canary jne .L5 mov ebx, DWORD PTR [ebp-4] leave ret .L5: call __stack_chk_fail Random value is located in gs:20. It is to be written on the stack and then, at the function end, value in the stack is compared with correct “canary” in gs:20. If values are not equal to each other, __stack_chk_fail function will be called and we will see something like that in console (Ubuntu 13.04 x86): *** buffer overflow detected ***: ./2_1 terminated ======= Backtrace: ========= /lib/i386-linux-gnu/libc.so.6(__fortify_fail+0x63)[0xb7699bc3] /lib/i386-linux-gnu/libc.so.6(+0x10593a)[0xb769893a] /lib/i386-linux-gnu/libc.so.6(+0x105008)[0xb7698008] /lib/i386-linux-gnu/libc.so.6(_IO_default_xsputn+0x8c)[0xb7606e5c] /lib/i386-linux-gnu/libc.so.6(_IO_vfprintf+0x165)[0xb75d7a45] /lib/i386-linux-gnu/libc.so.6(__vsprintf_chk+0xc9)[0xb76980d9] /lib/i386-linux-gnu/libc.so.6(__sprintf_chk+0x2f)[0xb7697fef] ./2_1[0x8048404] /lib/i386-linux-gnu/libc.so.6(__libc_start_main+0xf5)[0xb75ac935] ======= Memory map: ======== 08048000-08049000 r-xp 00000000 08:01 2097586 /home/dennis/2_1 08049000-0804a000 r--p 00000000 08:01 2097586 /home/dennis/2_1 0804a000-0804b000 rw-p 00001000 08:01 2097586 /home/dennis/2_1 094d1000-094f2000 rw-p 00000000 00:00 0 [heap] b7560000-b757b000 r-xp 00000000 08:01 1048602 /lib/i386-linux-gnu/libgcc_s.so.1 b757b000-b757c000 r--p 0001a000 08:01 1048602 /lib/i386-linux-gnu/libgcc_s.so.1 b757c000-b757d000 rw-p 0001b000 08:01 1048602 /lib/i386-linux-gnu/libgcc_s.so.1 b7592000-b7593000 rw-p 00000000 00:00 0 b7593000-b7740000 r-xp 00000000 08:01 1050781 /lib/i386-linux-gnu/libc-2.17.so b7740000-b7742000 r--p 001ad000 08:01 1050781 /lib/i386-linux-gnu/libc-2.17.so b7742000-b7743000 rw-p 001af000 08:01 1050781 /lib/i386-linux-gnu/libc-2.17.so b7743000-b7746000 rw-p 00000000 00:00 0 b775a000-b775d000 rw-p 00000000 00:00 0 b775d000-b775e000 r-xp 00000000 00:00 0 [vdso] b775e000-b777e000 r-xp 00000000 08:01 1050794 /lib/i386-linux-gnu/ld-2.17.so 132 16.3. BUFFER OVERFLOW PROTECTION METHODS CHAPTER 16. ARRAYS b777e000-b777f000 r--p 0001f000 08:01 1050794 /lib/i386-linux-gnu/ld-2.17.so b777f000-b7780000 rw-p 00020000 08:01 1050794 /lib/i386-linux-gnu/ld-2.17.so bff35000-bff56000 rw-p 00000000 00:00 0 [stack] Aborted (core dumped) gs—is so-called segment register, these registers were used widely in MS-DOS and DOS-extenders times. Today, its func- tion is dierent. If to say briefly, the gs register in Linux is always pointing to the TLS(45) —various information specific to thread is stored there (by the way, in win32 environment, the fs register plays the same role, it pointing to TIB89 ). More information can be found in Linux source codes (at least in 3.11 version), in arch/x86/include/asm/stackprotector.h file this variable is described in comments. 16.3.1 Optimizing Xcode (LLVM) + thumb-2 mode Let’s back to our simple array example (16.1), again, now we can see how LLVM will check “canary” correctness: _main var_64 = -0x64 var_60 = -0x60 var_5C = -0x5C var_58 = -0x58 var_54 = -0x54 var_50 = -0x50 var_4C = -0x4C var_48 = -0x48 var_44 = -0x44 var_40 = -0x40 var_3C = -0x3C var_38 = -0x38 var_34 = -0x34 var_30 = -0x30 var_2C = -0x2C var_28 = -0x28 var_24 = -0x24 var_20 = -0x20 var_1C = -0x1C var_18 = -0x18 canary = -0x14 var_10 = -0x10 PUSH {R4-R7,LR} ADD R7, SP, #0xC STR.W R8, [SP,#0xC+var_10]! SUB SP, SP, #0x54 MOVW R0, #aObjc_methtype ; "objc_methtype" MOVS R2, #0 MOVT.W R0, #0 MOVS R5, #0 ADD R0, PC LDR.W R8, [R0] LDR.W R0, [R8] STR R0, [SP,#0x64+canary] MOVS R0, #2 STR R2, [SP,#0x64+var_64] STR R0, [SP,#0x64+var_60] MOVS R0, #4 STR R0, [SP,#0x64+var_5C] MOVS R0, #6 STR R0, [SP,#0x64+var_58] 8Thread Information Block 9https://en.wikipedia.org/wiki/Win32_Thread_Information_Block 133 16.3. BUFFER OVERFLOW PROTECTION METHODS CHAPTER 16. ARRAYS MOVS R0, #8 STR R0, [SP,#0x64+var_54] MOVS R0, #0xA STR R0, [SP,#0x64+var_50] MOVS R0, #0xC STR R0, [SP,#0x64+var_4C] MOVS R0, #0xE STR R0, [SP,#0x64+var_48] MOVS R0, #0x10 STR R0, [SP,#0x64+var_44] MOVS R0, #0x12 STR R0, [SP,#0x64+var_40] MOVS R0, #0x14 STR R0, [SP,#0x64+var_3C] MOVS R0, #0x16 STR R0, [SP,#0x64+var_38] MOVS R0, #0x18 STR R0, [SP,#0x64+var_34] MOVS R0, #0x1A STR R0, [SP,#0x64+var_30] MOVS R0, #0x1C STR R0, [SP,#0x64+var_2C] MOVS R0, #0x1E STR R0, [SP,#0x64+var_28] MOVS R0, #0x20 STR R0, [SP,#0x64+var_24] MOVS R0, #0x22 STR R0, [SP,#0x64+var_20] MOVS R0, #0x24 STR R0, [SP,#0x64+var_1C] MOVS R0, #0x26 STR R0, [SP,#0x64+var_18] MOV R4, 0xFDA ; "a[%d]=%d\n" MOV R0, SP ADDS R6, R0, #4 ADD R4, PC B loc_2F1C ; second loop begin loc_2F14 ADDS R0, R5, #1 LDR.W R2, [R6,R5,LSL#2] MOV R5, R0 loc_2F1C MOV R0, R4 MOV R1, R5 BLX _printf CMP R5, #0x13 BNE loc_2F14 LDR.W R0, [R8] LDR R1, [SP,#0x64+canary] CMP R0, R1 ITTTT EQ ; canary still correct? MOVEQ R0, #0 ADDEQ SP, SP, #0x54 LDREQ.W R8, [SP+0x64+var_64],#4 POPEQ {R4-R7,PC} BLX ___stack_chk_fail 134 16.4. ONE MORE WORD ABOUT ARRAYS CHAPTER 16. ARRAYS First of all, as we see, LLVM made loop “unrolled” and all values are written into array one-by-one, already calculated since LLVM concluded it will be faster. By the way, ARM mode instructions may help to do this even faster, and finding this way could be your homework. At the function end wee see “canaries” comparison —that laying in local stack and correct one, to which the R8 register pointing. If they are equal to each other, 4-instruction block is triggered by “ITTTT EQ”, it is writing 0 into R0, function epilogue and exit. If “canaries” are not equal, block will not be triggered, and jump to ___stack_chk_fail function will be occurred, which, as I suppose, will halt execution. 16.4 One more word about arrays Now we understand, why it is impossible to write something like that in C/C++ code 10: void f(int size) { int a[size]; ... }; That’s just because compiler must know exact array size to allocate space for it in local stack layout or in data segment (in case of global variable) on compiling stage. If you need array of arbitrary size, allocate it by malloc(), then access allocated memory block as array of variables of type you need. Or use C99 standard feature [15, 6.7.5/2], but it will be looks like alloca() (4.2.4) internally. 16.5 Multidimensional arrays Internally, multidimensional array is essentially the same thing as linear array. Since computer memory in linear, it is one-dimensional array. But this one-dimensional array can be easily represented as multidimensional for convenience. For example, that is how 푎(︀3⌋︀(︀4⌋︀ array elements will be placed in one-dimensional array of 12 cells: [0][0] [0][1] [0][2] [0][3] [1][0] [1][1] [1][2] [1][3] [2][0] [2][1] [2][2] [2][3] That is how two-dimensional array with one-dimensional (memory) array index numbers can be represented: 0 1 2 3 4 5 6 7 8 9 10 11 So, in order to address elements we need, first multiply first index by 4 (matrix width) and then add second index. That’s called row-major order, and this method of arrays and matrices representation is used in at least in C/C++, Python. row-major order term in plain English language means: “first, write elements of first row, then second row ...and finally elements of last row”. Another method of representation called column-major order (array indices used in reverse order) and it is used at least in FORTRAN, MATLAB, R. column-major order term in plain English language means: “first, write elements of first column, then second column ...and finally elements of last column”. Same thing about multidimensional arrays. Let’s see: 10However, it is possible in C99 standard [15, 6.7.5/2]: GCC is actually do this by allocating array dynammically on the stack (like alloca() (4.2.4)) 135 16.5. MULTIDIMENSIONAL ARRAYS CHAPTER 16. ARRAYS Listing 16.4: simple example #include int a[10][20][30]; void insert(int x, int y, int z, int value) { a[x][y][z]=value; }; 16.5.1 x86 We got (MSVC 2010): Listing 16.5: MSVC 2010 _DATA SEGMENT COMM _a:DWORD:01770H _DATA ENDS PUBLIC _insert _TEXT SEGMENT _x$ = 8 ; size = 4 _y$ = 12 ; size = 4 _z$ = 16 ; size = 4 _value$ = 20 ; size = 4 _insert PROC push ebp mov ebp, esp mov eax, DWORD PTR _x$[ebp] imul eax, 2400 ; eax=600*4*x mov ecx, DWORD PTR _y$[ebp] imul ecx, 120 ; ecx=30*4*y lea edx, DWORD PTR _a[eax+ecx] ; edx=a + 600*4*x + 30*4*y mov eax, DWORD PTR _z$[ebp] mov ecx, DWORD PTR _value$[ebp] mov DWORD PTR [edx+eax*4], ecx ; *(edx+z*4)=value pop ebp ret 0 _insert ENDP _TEXT ENDS Nothing special. For index calculation, three input arguments are multiplying by formula 푎푑푑푟푒푠푠 = 600⋅4⋅푥+30⋅4⋅푦+4푧 to represent array as multidimensional. Do not forget the int type is 32-bit (4 bytes), so all coeicients must be multiplied by 4. Listing 16.6: GCC 4.4.1 public insert insert proc near x = dword ptr 8 y = dword ptr 0Ch z = dword ptr 10h value = dword ptr 14h push ebp mov ebp, esp push ebx mov ebx, [ebp+x] mov eax, [ebp+y] mov ecx, [ebp+z] lea edx, [eax+eax] ; edx=y*2 136 16.5. MULTIDIMENSIONAL ARRAYS CHAPTER 16. ARRAYS mov eax, edx ; eax=y*2 shl eax, 4 ; eax=(y*2)<<4 = y*2*16 = y*32 sub eax, edx ; eax=y*32 - y*2=y*30 imul edx, ebx, 600 ; edx=x*600 add eax, edx ; eax=eax+edx=y*30 + x*600 lea edx, [eax+ecx] ; edx=y*30 + x*600 + z mov eax, [ebp+value] mov dword ptr ds:a[edx*4], eax ; *(a+edx*4)=value pop ebx pop ebp retn insert endp GCC compiler does it dierently. For one of operations calculating (30푦), GCC produced a code without multiplication instruction. This is how it done: (푦 + 푦) ≪ 4 − (푦 + 푦) = (2푦) ≪ 4 − 2푦 = 2 ⋅ 16 ⋅ 푦 − 2푦 = 32푦 − 2푦 = 30푦. Thus, for 30푦 calculation, only one addition operation used, one bitwise shi operation and one subtraction operation. That works faster. 16.5.2 ARM + Non-optimizing Xcode (LLVM) + thumb mode Listing 16.7: Non-optimizing Xcode (LLVM) + thumb mode _insert value = -0x10 z = -0xC y = -8 x = -4 ; allocate place in local stack for 4 values of int type SUB SP, SP, #0x10 MOV R9, 0xFC2 ; a ADD R9, PC LDR.W R9, [R9] STR R0, [SP,#0x10+x] STR R1, [SP,#0x10+y] STR R2, [SP,#0x10+z] STR R3, [SP,#0x10+value] LDR R0, [SP,#0x10+value] LDR R1, [SP,#0x10+z] LDR R2, [SP,#0x10+y] LDR R3, [SP,#0x10+x] MOV R12, 2400 MUL.W R3, R3, R12 ADD R3, R9 MOV R9, 120 MUL.W R2, R2, R9 ADD R2, R3 LSLS R1, R1, #2 ; R1=R1<<2 ADD R1, R2 STR R0, [R1] ; R1 - address of array element ; deallocate place in local stack, allocated for 4 values of int type ADD SP, SP, #0x10 BX LR Non-optimizing LLVM saves all variables in local stack, however, it is redundant. Address of array element is calculated by formula we already figured out. 16.5.3 ARM + Optimizing Xcode (LLVM) + thumb mode Listing 16.8: Optimizing Xcode (LLVM) + thumb mode 137 16.5. MULTIDIMENSIONAL ARRAYS CHAPTER 16. ARRAYS _insert MOVW R9, #0x10FC MOV.W R12, #2400 MOVT.W R9, #0 RSB.W R1, R1, R1,LSL#4 ; R1 - y. R1=y<<4 - y = y*16 - y = y*15 ADD R9, PC ; R9 = pointer to a array LDR.W R9, [R9] MLA.W R0, R0, R12, R9 ; R0 - x, R12 - 2400, R9 - pointer to a. R0=x*2400 + ptr to a ADD.W R0, R0, R1,LSL#3 ; R0 = R0+R1<<3 = R0+R1*8 = x*2400 + ptr to a + y*15*8 = ; ptr to a + y*30*4 + x*600*4 STR.W R3, [R0,R2,LSL#2] ; R2 - z, R3 - value. address=R0+z*4 = ; ptr to a + y*30*4 + x*600*4 + z*4 BX LR Here is used tricks for replacing multiplication by shi , addition and subtraction we already considered. Here we also see new instruction for us: RSB (Reverse Subtract). It works just as SUB, but swapping operands with each other. Why? SUB, RSB, are those instructions, to the second operand of which shi coeicient may be applied: (LSL#4). But this coeicient may be applied only to second operand. That’s fine for commutative operations like addition or multiplication, operands may be swapped there without result aecting. But subtraction is non-commutative operation, so, for these cases, RSB exist. “LDR.W R9, [R9]” works like LEA (B.6.2) in x86, but here it does nothing, it is redundant. Apparently, compiler not optimized it. 138 CHAPTER 17. BIT FIELDS Chapter 17 Bit fields A lot of functions defining input flags in arguments using bit fields. Of course, it could be substituted by bool-typed variables set, but it is not frugally. 17.1 Specific bit checking 17.1.1 x86 Win32 API example: HANDLE fh; fh=CreateFile ("file", GENERIC_WRITE | GENERIC_READ, FILE_SHARE_READ, NULL, OPEN_ALWAYS⤦ Ç, FILE_ATTRIBUTE_NORMAL, NULL); We got (MSVC 2010): Listing 17.1: MSVC 2010 push 0 push 128 ; 00000080H push 4 push 0 push 1 push -1073741824 ; c0000000H push OFFSET $SG78813 call DWORD PTR __imp__CreateFileA@28 mov DWORD PTR _fh$[ebp], eax Let’s take a look into WinNT.h: Listing 17.2: WinNT.h #define GENERIC_READ (0x80000000L) #define GENERIC_WRITE (0x40000000L) #define GENERIC_EXECUTE (0x20000000L) #define GENERIC_ALL (0x10000000L) Everything is clear,GENERIC_READ | GENERIC_WRITE = 0x80000000 | 0x40000000 = 0xC0000000, and that is value is used as the second argument for CreateFile()1 function. How CreateFile() will check flags? Let’s take a look into KERNEL32.DLL in Windows XP SP3 x86 and we’ll find this fragment of code in the functionCreateFileW: Listing 17.3: KERNEL32.DLL (Windows XP SP3 x86) .text:7C83D429 test byte ptr [ebp+dwDesiredAccess+3], 40h .text:7C83D42D mov [ebp+var_8], 1 .text:7C83D434 jz short loc_7C83D417 .text:7C83D436 jmp loc_7C810817 1MSDN: CreateFile function 139 17.1. SPECIFIC BIT CHECKING CHAPTER 17. BIT FIELDS Here we seeTESTinstruction, it takes, however, not the whole second argument, but only most significant byte (ebp+dwDesiredAccess+3) and checks it for 0x40 flag (meaning GENERIC_WRITE flag here) TEST is merely the same instruction as AND, but without result saving (recall the fact CMP instruction is merely the same as SUB, but without result saving (6.6.1)). This fragment of code logic is as follows: if ((dwDesiredAccess&0x40000000) == 0) goto loc_7C83D417 If AND instruction leaving this bit, ZF flag is to be cleared and JZ conditional jump will not be triggered. Conditional jump will be triggered only if 0x40000000 bit is absent in the dwDesiredAccess variable —then AND result will be 0, ZF flag will be set and conditional jump is to be triggered. Let’s try GCC 4.4.1 and Linux: #include #include void main() { int handle; handle=open ("file", O_RDWR | O_CREAT); }; We got: Listing 17.4: GCC 4.4.1 public main main proc near var_20 = dword ptr -20h var_1C = dword ptr -1Ch var_4 = dword ptr -4 push ebp mov ebp, esp and esp, 0FFFFFFF0h sub esp, 20h mov [esp+20h+var_1C], 42h mov [esp+20h+var_20], offset aFile ; "file" call _open mov [esp+20h+var_4], eax leave retn main endp Let’s take a look into open() function in the libc.so.6 library, but there is only syscall calling: Listing 17.5: open() (libc.so.6) .text:000BE69B mov edx, [esp+4+mode] ; mode .text:000BE69F mov ecx, [esp+4+flags] ; flags .text:000BE6A3 mov ebx, [esp+4+filename] ; filename .text:000BE6A7 mov eax, 5 .text:000BE6AC int 80h ; LINUX - sys_open So, open() bit fields apparently checked somewhere in Linux kernel. Of course, it is easily to download both Glibc and Linux kernel source code, but we are interesting to understand the matter without it. So, as of Linux 2.6, when sys_open syscall is called, control eventually passed into do_sys_open kernel function. From there —to the do_filp_open() function (this function located in kernel source tree in the file fs/namei.c). N.B. Aside from common passing arguments via stack, there is also a method of passing some of them via registers. This is also called fastcall (44.3). This works faster since CPU not needed to access a stack in memory to read argument values. GCC has option regparm2, and it is possible to set a number of arguments which might be passed via registers. 2http://ohse.de/uwe/articles/gcc-attributes.html#func-regparm 140 17.1. SPECIFIC BIT CHECKING CHAPTER 17. BIT FIELDS Linux 2.6 kernel compiled with -mregparm=3 option 34 . What it means to us, the first 3 arguments will be passed via EAX, EDX and ECX registers, the rest ones via stack. Of course, if arguments number is less than 3, only part of registers are to be used. So, let’s download Linux Kernel 2.6.31, compile it in Ubuntu: make vmlinux, open it in IDA, find the do_filp_open() function. At the beginning, we will see (comments are mine): Listing 17.6: do_filp_open() (linux kernel 2.6.31) do_filp_open proc near ... push ebp mov ebp, esp push edi push esi push ebx mov ebx, ecx add ebx, 1 sub esp, 98h mov esi, [ebp+arg_4] ; acc_mode (5th arg) test bl, 3 mov [ebp+var_80], eax ; dfd (1th arg) mov [ebp+var_7C], edx ; pathname (2th arg) mov [ebp+var_78], ecx ; open_flag (3th arg) jnz short loc_C01EF684 mov ebx, ecx ; ebx <- open_flag GCC saves first 3 arguments values in local stack. Otherwise, if compiler would not touch these registers, it would be too tight environment for compiler’s register allocator. Let’s find this fragment of code: Listing 17.7: do_filp_open() (linux kernel 2.6.31) loc_C01EF6B4: ; CODE XREF: do_filp_open+4F test bl, 40h ; O_CREAT jnz loc_C01EF810 mov edi, ebx shr edi, 11h xor edi, 1 and edi, 1 test ebx, 10000h jz short loc_C01EF6D3 or edi, 2 0x40—is whatO_CREATmacro equals to. open_flagchecked for0x40bit presence, and if this bit is1, nextJNZinstruction is triggered. 17.1.2 ARM O_CREAT bit is checked dierently in Linux kernel 3.8.0. Listing 17.8: linux kernel 3.8.0 struct file *do_filp_open(int dfd, struct filename *pathname, const struct open_flags *op) { ... filp = path_openat(dfd, pathname, &nd, op, flags | LOOKUP_RCU); ... } static struct file *path_openat(int dfd, struct filename *pathname, struct nameidata *nd, const struct open_flags *op, int flags) 3http://kernelnewbies.org/Linux_2_6_20#head-042c62f290834eb1fe0a1942bbf5bb9a4accbc8f 4See also arch\x86\include\asm\calling.h file in kernel tree 141 17.1. SPECIFIC BIT CHECKING CHAPTER 17. BIT FIELDS { ... error = do_last(nd, &path, file, op, &opened, pathname); ... } static int do_last(struct nameidata *nd, struct path *path, struct file *file, const struct open_flags *op, int *opened, struct filename *name) { ... if (!(open_flag & O_CREAT)) { ... error = lookup_fast(nd, path, &inode); ... } else { ... error = complete_walk(nd); } ... } Here is how kernel compiled for ARM mode looks like in IDA: Listing 17.9: do_last() (vmlinux) ... .text:C0169EA8 MOV R9, R3 ; R3 - (4th argument) open_flag ... .text:C0169ED4 LDR R6, [R9] ; R6 - open_flag ... .text:C0169F68 TST R6, #0x40 ; jumptable C0169F00 default case .text:C0169F6C BNE loc_C016A128 .text:C0169F70 LDR R2, [R4,#0x10] .text:C0169F74 ADD R12, R4, #8 .text:C0169F78 LDR R3, [R4,#0xC] .text:C0169F7C MOV R0, R4 .text:C0169F80 STR R12, [R11,#var_50] .text:C0169F84 LDRB R3, [R2,R3] .text:C0169F88 MOV R2, R8 .text:C0169F8C CMP R3, #0 .text:C0169F90 ORRNE R1, R1, #3 .text:C0169F94 STRNE R1, [R4,#0x24] .text:C0169F98 ANDS R3, R6, #0x200000 .text:C0169F9C MOV R1, R12 .text:C0169FA0 LDRNE R3, [R4,#0x24] .text:C0169FA4 ANDNE R3, R3, #1 .text:C0169FA8 EORNE R3, R3, #1 .text:C0169FAC STR R3, [R11,#var_54] .text:C0169FB0 SUB R3, R11, #-var_38 .text:C0169FB4 BL lookup_fast ... .text:C016A128 loc_C016A128 ; CODE XREF: do_last.isra.14+DC .text:C016A128 MOV R0, R4 .text:C016A12C BL complete_walk ... TST is analogical to a TEST instruction in x86. We can “spot” visually this code fragment by the fact thelookup_fast()will be executed in one case and thecomplete_walk() in another case. This is corresponding to the do_last() function source code. O_CREAT macro is equals to 0x40 here too. 142 17.2. SPECIFIC BIT SETTING/CLEARING CHAPTER 17. BIT FIELDS 17.2 Specific bit setting/clearing For example: #define IS_SET(flag, bit) ((flag) & (bit)) #define SET_BIT(var, bit) ((var) |= (bit)) #define REMOVE_BIT(var, bit) ((var) &= ~(bit)) int f(int a) { int rt=a; SET_BIT (rt, 0x4000); REMOVE_BIT (rt, 0x200); return rt; }; 17.2.1 x86 We got (MSVC 2010): Listing 17.10: MSVC 2010 _rt$ = -4 ; size = 4 _a$ = 8 ; size = 4 _f PROC push ebp mov ebp, esp push ecx mov eax, DWORD PTR _a$[ebp] mov DWORD PTR _rt$[ebp], eax mov ecx, DWORD PTR _rt$[ebp] or ecx, 16384 ; 00004000H mov DWORD PTR _rt$[ebp], ecx mov edx, DWORD PTR _rt$[ebp] and edx, -513 ; fffffdffH mov DWORD PTR _rt$[ebp], edx mov eax, DWORD PTR _rt$[ebp] mov esp, ebp pop ebp ret 0 _f ENDP OR instruction adds one more bit to value while ignoring the rest ones. AND resetting one bit. It can be said, AND just copies all bits except one. Indeed, in the second AND operand only those bits are set, which are needed to be saved, except one bit we would not like to copy (which is 0 in bitmask). It is easier way to memorize the logic. If we compile it in MSVC with optimization turned on (/Ox), the code will be even shorter: Listing 17.11: Optimizing MSVC _a$ = 8 ; size = 4 _f PROC mov eax, DWORD PTR _a$[esp-4] and eax, -513 ; fffffdffH or eax, 16384 ; 00004000H ret 0 _f ENDP Let’s try GCC 4.4.1 without optimization: Listing 17.12: Non-optimizing GCC 143 17.2. SPECIFIC BIT SETTING/CLEARING CHAPTER 17. BIT FIELDS public f f proc near var_4 = dword ptr -4 arg_0 = dword ptr 8 push ebp mov ebp, esp sub esp, 10h mov eax, [ebp+arg_0] mov [ebp+var_4], eax or [ebp+var_4], 4000h and [ebp+var_4], 0FFFFFDFFh mov eax, [ebp+var_4] leave retn f endp There is a redundant code present, however, it is shorter then MSVC version without optimization. Now let’s try GCC with optimization turned on -O3: Listing 17.13: Optimizing GCC public f f proc near arg_0 = dword ptr 8 push ebp mov ebp, esp mov eax, [ebp+arg_0] pop ebp or ah, 40h and ah, 0FDh retn f endp That’s shorter. It is worth noting the compiler works with the EAX register part via the AH register —that is the EAX register part from 8th to 15th bits inclusive. 7th (byte number) 6th 5th 4th 3rd 2nd 1st 0th RAXx64 EAX AX AH AL N.B. 16-bit CPU 8086 accumulator was named AX and consisted of two 8-bit halves —AL (lower byte) and AH (higher byte). In 80386 almost all registers were extended to 32-bit, accumulator was named EAX, but for the sake of compatibility, its older parts may be still accessed as AX/AH/AL registers. Since all x86 CPUs are 16-bit 8086 CPU successors, these older 16-bit opcodes are shorter than newer 32-bit opcodes. That’s why “or ah, 40h” instruction occupying only 3 bytes. It would be more logical way to emit here “or eax, 04000h” but that is 5 bytes, or even 6 (in case if register in first operand is not EAX). It would be even shorter if to turn on -O3 optimization flag and also set regparm=3. Listing 17.14: Optimizing GCC public f f proc near push ebp or ah, 40h mov ebp, esp and ah, 0FDh pop ebp retn 144 17.3. SHIFTS CHAPTER 17. BIT FIELDS f endp Indeed —first argument is already loaded into EAX, so it is possible to work with it in-place. It is worth noting that both function prologue (“push ebp / mov ebp,esp”) and epilogue (“pop ebp”) can easily be omitted here, but GCC probably is not good enough for such code size optimizations. However, such short functions are better to be inlined functions (27). 17.2.2 ARM + Optimizing Keil + ARM mode Listing 17.15: Optimizing Keil + ARM mode 02 0C C0 E3 BIC R0, R0, #0x200 01 09 80 E3 ORR R0, R0, #0x4000 1E FF 2F E1 BX LR BIC is “logical and”, analogical to AND in x86. ORR is “logical or”, analogical to OR in x86. So far, so easy. 17.2.3 ARM + Optimizing Keil + thumb mode Listing 17.16: Optimizing Keil + thumb mode 01 21 89 03 MOVS R1, 0x4000 08 43 ORRS R0, R1 49 11 ASRS R1, R1, #5 ; generate 0x200 and place to R1 88 43 BICS R0, R1 70 47 BX LR Apparently, Keil concludes the code in thumb mode, making0x200from0x4000, will be more compact than code, writing 0x200 to arbitrary register. So that is why, with the help of ASRS (arithmetic shi right), this value is calculating as 0x4000 ≫ 5. 17.2.4 ARM + Optimizing Xcode (LLVM) + ARM mode Listing 17.17: Optimizing Xcode (LLVM) + ARM mode 42 0C C0 E3 BIC R0, R0, #0x4200 01 09 80 E3 ORR R0, R0, #0x4000 1E FF 2F E1 BX LR The code was generated by LLVM, in source code form, in fact, could be looks like: REMOVE_BIT (rt, 0x4200); SET_BIT (rt, 0x4000); And it does exactly the same we need. But why 0x4200? Perhaps, that is the LLVM optimizer’s artifact 5. Probably, com- piler’s optimizer error, but generated code works correct anyway. More about compiler’s anomalies, read here (64). For thumb mode, Optimizing Xcode (LLVM) generates likewise code. 17.3 Shi s Bit shi s in C/C++ are implemented via ≪ and ≫ operators. Here is a simple example of function, calculating number of 1 bits in input variable: #define IS_SET(flag, bit) ((flag) & (bit)) int f(unsigned int a) { int i; int rt=0; 5It was LLVM build 2410.2.00 bundled with Apple Xcode 4.6.3 145 17.3. SHIFTS CHAPTER 17. BIT FIELDS for (i=0; i<32; i++) if (IS_SET (a, 1< #include #include typedef unsigned long ub4; typedef unsigned char ub1; static const ub4 crctab[256] = { 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d, }; /* how to derive the values in crctab[] from polynomial 0xedb88320 */ void build_table() { ub4 i, j; for (i=0; i<256; ++i) { 149 17.4. CRC32 CALCULATION EXAMPLE CHAPTER 17. BIT FIELDS j = i; j = (j>>1) ^ ((j&1) ? 0xedb88320 : 0); j = (j>>1) ^ ((j&1) ? 0xedb88320 : 0); j = (j>>1) ^ ((j&1) ? 0xedb88320 : 0); j = (j>>1) ^ ((j&1) ? 0xedb88320 : 0); j = (j>>1) ^ ((j&1) ? 0xedb88320 : 0); j = (j>>1) ^ ((j&1) ? 0xedb88320 : 0); j = (j>>1) ^ ((j&1) ? 0xedb88320 : 0); j = (j>>1) ^ ((j&1) ? 0xedb88320 : 0); printf("0x%.8lx, ", j); if (i%6 == 5) printf("\n"); } } /* the hash function */ ub4 crc(const void *key, ub4 len, ub4 hash) { ub4 i; const ub1 *k = key; for (hash=len, i=0; i> 8) ^ crctab[(hash & 0xff) ^ k[i]]; return hash; } /* To use, try "gcc -O crc.c -o crc; crc < crc.c" */ int main() { char s[1000]; while (gets(s)) printf("%.8lx\n", crc(s, strlen(s), 0)); return 0; } We are interesting in the crc() function only. By the way, pay attention to two loop initializers in the for() statement: hash=len, i=0. C/C++ standard allows this, of course. Emitted code will contain two operations in loop initialization part instead of usual one. Let’s compile it in MSVC with optimization (/Ox). For the sake of brevity, only crc() function is listed here, with my comments. _key$ = 8 ; size = 4 _len$ = 12 ; size = 4 _hash$ = 16 ; size = 4 _crc PROC mov edx, DWORD PTR _len$[esp-4] xor ecx, ecx ; i will be stored in ECX mov eax, edx test edx, edx jbe SHORT $LN1@crc push ebx push esi mov esi, DWORD PTR _key$[esp+4] ; ESI = key push edi $LL3@crc: ; work with bytes using only 32-bit registers. byte from address key+i we store into EDI movzx edi, BYTE PTR [ecx+esi] mov ebx, eax ; EBX = (hash = len) and ebx, 255 ; EBX = hash & 0xff ; XOR EDI, EBX (EDI=EDI^EBX) - this operation uses all 32 bits of each register ; but other bits (8-31) are cleared all time, so it’s OK 150 17.4. CRC32 CALCULATION EXAMPLE CHAPTER 17. BIT FIELDS ; these are cleared because, as for EDI, it was done by MOVZX instruction above ; high bits of EBX was cleared by AND EBX, 255 instruction above (255 = 0xff) xor edi, ebx ; EAX=EAX>>8; bits 24-31 taken "from nowhere" will be cleared shr eax, 8 ; EAX=EAX^crctab[EDI*4] - choose EDI-th element from crctab[] table xor eax, DWORD PTR _crctab[edi*4] inc ecx ; i++ cmp ecx, edx ; i>8 movzx eax, al ; EAX=*(key+i) mov eax, dword ptr ds:crctab[eax*4] ; EAX=crctab[EAX] xor eax, ecx ; hash=EAX^ECX cmp ebx, edx ja short loc_80484B8 loc_80484D3: pop ebx pop esi pop ebp retn crc endp \ GCC aligned loop start on a 8-byte boundary by adding NOP and lea esi, [esi+0] (that is the idle operation too). Read more about it in npad section (61). 151 CHAPTER 18. STRUCTURES Chapter 18 Structures It can be defined the C/C++ structure, with some assumptions, just a set of variables, always stored in memory together, not necessary of the same type 1. 18.1 SYSTEMTIME example Let’s take SYSTEMTIME2 win32 structure describing time. That’s how it is defined: Listing 18.1: WinBase.h typedef struct _SYSTEMTIME { WORD wYear; WORD wMonth; WORD wDayOfWeek; WORD wDay; WORD wHour; WORD wMinute; WORD wSecond; WORD wMilliseconds; } SYSTEMTIME, *PSYSTEMTIME; Let’s write a C function to get current time: #include #include void main() { SYSTEMTIME t; GetSystemTime (&t); printf ("%04d-%02d-%02d %02d:%02d:%02d\n", t.wYear, t.wMonth, t.wDay, t.wHour, t.wMinute, t.wSecond); return; }; We got (MSVC 2010): Listing 18.2: MSVC 2010 _t$ = -16 ; size = 16 _main PROC push ebp mov ebp, esp 1AKA “heterogeneous container” 2MSDN: SYSTEMTIME structure 152 18.1. SYSTEMTIME EXAMPLE CHAPTER 18. STRUCTURES sub esp, 16 lea eax, DWORD PTR _t$[ebp] push eax call DWORD PTR __imp__GetSystemTime@4 movzx ecx, WORD PTR _t$[ebp+12] ; wSecond push ecx movzx edx, WORD PTR _t$[ebp+10] ; wMinute push edx movzx eax, WORD PTR _t$[ebp+8] ; wHour push eax movzx ecx, WORD PTR _t$[ebp+6] ; wDay push ecx movzx edx, WORD PTR _t$[ebp+2] ; wMonth push edx movzx eax, WORD PTR _t$[ebp] ; wYear push eax push OFFSET $SG78811 ; ’%04d-%02d-%02d %02d:%02d:%02d’, 0aH, 00H call _printf add esp, 28 xor eax, eax mov esp, ebp pop ebp ret 0 _main ENDP 16 bytes are allocated for this structure in local stack —that is exactly sizeof(WORD)*8 (there are 8 WORD variables in the structure). Pay attention to the fact the structure beginning with wYear field. It can be said, an pointer to SYSTEMTIME structure is passed to the GetSystemTime()3, but it is also can be said, pointer to the wYear field is passed, and that is the same! GetSystemTime() writes current year to the WORD pointer pointing to, then shi s 2 bytes ahead, then writes current month, etc, etc. The fact the structure fields are just variables located side-by-side, I can demonstrate by the following technique. Keeping in ming SYSTEMTIME structure description, I can rewrite this simple example like this: #include #include void main() { WORD array[8]; GetSystemTime (array); printf ("%04d-%02d-%02d %02d:%02d:%02d\n", array[0] /* wYear */, array[1] /* wMonth */, array[3] /* wDay */, array[4] /* wHour */, array[5] /* wMinute */, array[6] /* wSecond */); return; }; Compiler will grumble for a little: systemtime2.c(7) : warning C4133: ’function’ : incompatible types - from ’WORD [8]’ to ’⤦ Ç LPSYSTEMTIME’ But nevertheless, it will produce this code: Listing 18.3: MSVC 2010 $SG78573 DB ’%04d-%02d-%02d %02d:%02d:%02d’, 0aH, 00H _array$ = -16 ; size = 16 _main PROC 3MSDN: SYSTEMTIME structure 153 18.2. LET’S ALLOCATE SPACE FOR STRUCTURE USING MALLOC() CHAPTER 18. STRUCTURES push ebp mov ebp, esp sub esp, 16 lea eax, DWORD PTR _array$[ebp] push eax call DWORD PTR __imp__GetSystemTime@4 movzx ecx, WORD PTR _array$[ebp+12] ; wSecond push ecx movzx edx, WORD PTR _array$[ebp+10] ; wMinute push edx movzx eax, WORD PTR _array$[ebp+8] ; wHoure push eax movzx ecx, WORD PTR _array$[ebp+6] ; wDay push ecx movzx edx, WORD PTR _array$[ebp+2] ; wMonth push edx movzx eax, WORD PTR _array$[ebp] ; wYear push eax push OFFSET $SG78573 call _printf add esp, 28 xor eax, eax mov esp, ebp pop ebp ret 0 _main ENDP And it works just as the same! It is very interesting fact the result in assembly form cannot be distinguished from the result of previous compilation. So by looking at this code, one cannot say for sure, was there structure declared, or just pack of variables. Nevertheless, no one will do it in sane state of mind. Since it is not convenient. Also structure fields may be changed by developers, swapped, etc. 18.2 Let’s allocate space for structure using malloc() However, sometimes it is simpler to place structures not in local stack, but in heap: #include #include void main() { SYSTEMTIME *t; t=(SYSTEMTIME *)malloc (sizeof (SYSTEMTIME)); GetSystemTime (t); printf ("%04d-%02d-%02d %02d:%02d:%02d\n", t->wYear, t->wMonth, t->wDay, t->wHour, t->wMinute, t->wSecond); free (t); return; }; Let’s compile it now with optimization (/Ox) so to easily see what we need. Listing 18.4: Optimizing MSVC _main PROC 154 18.2. LET’S ALLOCATE SPACE FOR STRUCTURE USING MALLOC() CHAPTER 18. STRUCTURES push esi push 16 call _malloc add esp, 4 mov esi, eax push esi call DWORD PTR __imp__GetSystemTime@4 movzx eax, WORD PTR [esi+12] ; wSecond movzx ecx, WORD PTR [esi+10] ; wMinute movzx edx, WORD PTR [esi+8] ; wHour push eax movzx eax, WORD PTR [esi+6] ; wDay push ecx movzx ecx, WORD PTR [esi+2] ; wMonth push edx movzx edx, WORD PTR [esi] ; wYear push eax push ecx push edx push OFFSET $SG78833 call _printf push esi call _free add esp, 32 xor eax, eax pop esi ret 0 _main ENDP So, sizeof(SYSTEMTIME) = 16, that is exact number of bytes to be allocated by malloc(). It returns the pointer to freshly allocated memory block in the EAX register, which is then moved into the ESI register. GetSystemTime() win32 func- tion undertake to save value in the ESI, and that is why it is not saved here and continue to be used a er GetSystemTime() call. New instruction —MOVZX (Move with Zero eXtent). It may be used almost in those cases as MOVSX (13.1.1), but, it clears other bits to 0. That’s because printf() requires 32-bit int, but we got WORD in structure —that is 16-bit unsigned type. That’s why by copying value from WORD into int, bits from 16 to 31 must also be cleared, because there will be random noise otherwise, leaved there from previous operations on registers. In this example, I can represent structure as array of WORD-s: #include #include void main() { WORD *t; t=(WORD *)malloc (16); GetSystemTime (t); printf ("%04d-%02d-%02d %02d:%02d:%02d\n", t[0] /* wYear */, t[1] /* wMonth */, t[3] /* wDay */, t[4] /* wHour */, t[5] /* wMinute */, t[6] /* wSecond */); free (t); return; }; We got: Listing 18.5: Optimizing MSVC 155 18.3. STRUCT TM CHAPTER 18. STRUCTURES $SG78594 DB ’%04d-%02d-%02d %02d:%02d:%02d’, 0aH, 00H _main PROC push esi push 16 call _malloc add esp, 4 mov esi, eax push esi call DWORD PTR __imp__GetSystemTime@4 movzx eax, WORD PTR [esi+12] movzx ecx, WORD PTR [esi+10] movzx edx, WORD PTR [esi+8] push eax movzx eax, WORD PTR [esi+6] push ecx movzx ecx, WORD PTR [esi+2] push edx movzx edx, WORD PTR [esi] push eax push ecx push edx push OFFSET $SG78594 call _printf push esi call _free add esp, 32 xor eax, eax pop esi ret 0 _main ENDP Again, we got the code cannot be distinguished from the previous. And again I should note, one should not do this in practice. 18.3 struct tm 18.3.1 Linux As of Linux, let’s take tm structure from time.h for example: #include #include void main() { struct tm t; time_t unix_time; unix_time=time(NULL); localtime_r (&unix_time, &t); printf ("Year: %d\n", t.tm_year+1900); printf ("Month: %d\n", t.tm_mon); printf ("Day: %d\n", t.tm_mday); printf ("Hour: %d\n", t.tm_hour); printf ("Minutes: %d\n", t.tm_min); printf ("Seconds: %d\n", t.tm_sec); }; Let’s compile it in GCC 4.4.1: 156 18.3. STRUCT TM CHAPTER 18. STRUCTURES Listing 18.6: GCC 4.4.1 main proc near push ebp mov ebp, esp and esp, 0FFFFFFF0h sub esp, 40h mov dword ptr [esp], 0 ; first argument for time() call time mov [esp+3Ch], eax lea eax, [esp+3Ch] ; take pointer to what time() returned lea edx, [esp+10h] ; at ESP+10h struct tm will begin mov [esp+4], edx ; pass pointer to the structure begin mov [esp], eax ; pass pointer to result of time() call localtime_r mov eax, [esp+24h] ; tm_year lea edx, [eax+76Ch] ; edx=eax+1900 mov eax, offset format ; "Year: %d\n" mov [esp+4], edx mov [esp], eax call printf mov edx, [esp+20h] ; tm_mon mov eax, offset aMonthD ; "Month: %d\n" mov [esp+4], edx mov [esp], eax call printf mov edx, [esp+1Ch] ; tm_mday mov eax, offset aDayD ; "Day: %d\n" mov [esp+4], edx mov [esp], eax call printf mov edx, [esp+18h] ; tm_hour mov eax, offset aHourD ; "Hour: %d\n" mov [esp+4], edx mov [esp], eax call printf mov edx, [esp+14h] ; tm_min mov eax, offset aMinutesD ; "Minutes: %d\n" mov [esp+4], edx mov [esp], eax call printf mov edx, [esp+10h] mov eax, offset aSecondsD ; "Seconds: %d\n" mov [esp+4], edx ; tm_sec mov [esp], eax call printf leave retn main endp Somehow, IDA did not created local variables names in local stack. But since we already experienced reverse engineers :-) we may do it without this information in this simple example. Please also pay attention to the lea edx, [eax+76Ch] —this instruction just adding 0x76C to value in the EAX, but not modifies any flags. See also relevant section about LEA (B.6.2). In order to illustrate the structure is just variables laying side-by-side in one place, let’s rework example, while looking at the file time.h: Listing 18.7: time.h struct tm { int tm_sec; int tm_min; 157 18.3. STRUCT TM CHAPTER 18. STRUCTURES int tm_hour; int tm_mday; int tm_mon; int tm_year; int tm_wday; int tm_yday; int tm_isdst; }; #include #include void main() { int tm_sec, tm_min, tm_hour, tm_mday, tm_mon, tm_year, tm_wday, tm_yday, tm_isdst; time_t unix_time; unix_time=time(NULL); localtime_r (&unix_time, &tm_sec); printf ("Year: %d\n", tm_year+1900); printf ("Month: %d\n", tm_mon); printf ("Day: %d\n", tm_mday); printf ("Hour: %d\n", tm_hour); printf ("Minutes: %d\n", tm_min); printf ("Seconds: %d\n", tm_sec); }; N.B. The pointer to the exactly tm_sec field is passed into localtime_r, i.e., to the first “structure” element. Compiler will warn us: Listing 18.8: GCC 4.7.3 GCC_tm2.c: In function ’main’: GCC_tm2.c:11:5: warning: passing argument 2 of ’localtime_r’ from incompatible pointer type [⤦ Ç enabled by default] In file included from GCC_tm2.c:2:0: /usr/include/time.h:59:12: note: expected ’struct tm *’ but argument is of type ’int *’ But nevertheless, will generate this: Listing 18.9: GCC 4.7.3 main proc near var_30 = dword ptr -30h var_2C = dword ptr -2Ch unix_time = dword ptr -1Ch tm_sec = dword ptr -18h tm_min = dword ptr -14h tm_hour = dword ptr -10h tm_mday = dword ptr -0Ch tm_mon = dword ptr -8 tm_year = dword ptr -4 push ebp mov ebp, esp and esp, 0FFFFFFF0h sub esp, 30h call __main mov [esp+30h+var_30], 0 ; arg 0 call time 158 18.3. STRUCT TM CHAPTER 18. STRUCTURES mov [esp+30h+unix_time], eax lea eax, [esp+30h+tm_sec] mov [esp+30h+var_2C], eax lea eax, [esp+30h+unix_time] mov [esp+30h+var_30], eax call localtime_r mov eax, [esp+30h+tm_year] add eax, 1900 mov [esp+30h+var_2C], eax mov [esp+30h+var_30], offset aYearD ; "Year: %d\n" call printf mov eax, [esp+30h+tm_mon] mov [esp+30h+var_2C], eax mov [esp+30h+var_30], offset aMonthD ; "Month: %d\n" call printf mov eax, [esp+30h+tm_mday] mov [esp+30h+var_2C], eax mov [esp+30h+var_30], offset aDayD ; "Day: %d\n" call printf mov eax, [esp+30h+tm_hour] mov [esp+30h+var_2C], eax mov [esp+30h+var_30], offset aHourD ; "Hour: %d\n" call printf mov eax, [esp+30h+tm_min] mov [esp+30h+var_2C], eax mov [esp+30h+var_30], offset aMinutesD ; "Minutes: %d\n" call printf mov eax, [esp+30h+tm_sec] mov [esp+30h+var_2C], eax mov [esp+30h+var_30], offset aSecondsD ; "Seconds: %d\n" call printf leave retn main endp This code is identical to what we saw previously and it is not possible to say, was it structure in original source code or just pack of variables. And this works. However, it is not recommended to do this in practice. Usually, compiler allocated variables in local stack in the same order as they were declared in function. Nevertheless, there is no any guarantee. By the way, some other compiler may warn the tm_year, tm_mon, tm_mday, tm_hour, tm_min variables, but not tm_sec are used without being initialized. Indeed, compiler do not know these will be filled when calling to localtime_r(). I chose exactly this example for illustration, since all structure fields has int type, and SYSTEMTIME structure fields —16- bit WORD, and if to declare them as a local variables, they will be aligned on a 32-bit border, and nothing will work (because GetSystemTime() will fill them incorrectly). Read more about it in next section: “Fields packing in structure”. So, structure is just variables pack laying on one place, side-by-side. I could say the structure is a syntactic sugar, directing compiler to hold them in one place. However, I’m not programming languages expert, so, most likely, I’m wrong with this term. By the way, there were a times, in very early C versions (before 1972), in which there were no structures at all [29]. 18.3.2 ARM + Optimizing Keil + thumb mode Same example: Listing 18.10: Optimizing Keil + thumb mode var_38 = -0x38 var_34 = -0x34 var_30 = -0x30 var_2C = -0x2C var_28 = -0x28 var_24 = -0x24 timer = -0xC 159 18.3. STRUCT TM CHAPTER 18. STRUCTURES PUSH {LR} MOVS R0, #0 ; timer SUB SP, SP, #0x34 BL time STR R0, [SP,#0x38+timer] MOV R1, SP ; tp ADD R0, SP, #0x38+timer ; timer BL localtime_r LDR R1, =0x76C LDR R0, [SP,#0x38+var_24] ADDS R1, R0, R1 ADR R0, aYearD ; "Year: %d\n" BL __2printf LDR R1, [SP,#0x38+var_28] ADR R0, aMonthD ; "Month: %d\n" BL __2printf LDR R1, [SP,#0x38+var_2C] ADR R0, aDayD ; "Day: %d\n" BL __2printf LDR R1, [SP,#0x38+var_30] ADR R0, aHourD ; "Hour: %d\n" BL __2printf LDR R1, [SP,#0x38+var_34] ADR R0, aMinutesD ; "Minutes: %d\n" BL __2printf LDR R1, [SP,#0x38+var_38] ADR R0, aSecondsD ; "Seconds: %d\n" BL __2printf ADD SP, SP, #0x34 POP {PC} 18.3.3 ARM + Optimizing Xcode (LLVM) + thumb-2 mode IDA “get to know” tm structure (because IDA “knows” argument types of library functions like localtime_r()), so it shows here structure elements accesses and also names are assigned to them. Listing 18.11: Optimizing Xcode (LLVM) + thumb-2 mode var_38 = -0x38 var_34 = -0x34 PUSH {R7,LR} MOV R7, SP SUB SP, SP, #0x30 MOVS R0, #0 ; time_t * BLX _time ADD R1, SP, #0x38+var_34 ; struct tm * STR R0, [SP,#0x38+var_38] MOV R0, SP ; time_t * BLX _localtime_r LDR R1, [SP,#0x38+var_34.tm_year] MOV R0, 0xF44 ; "Year: %d\n" ADD R0, PC ; char * ADDW R1, R1, #0x76C BLX _printf LDR R1, [SP,#0x38+var_34.tm_mon] MOV R0, 0xF3A ; "Month: %d\n" ADD R0, PC ; char * BLX _printf LDR R1, [SP,#0x38+var_34.tm_mday] MOV R0, 0xF35 ; "Day: %d\n" 160 18.4. FIELDS PACKING IN STRUCTURE CHAPTER 18. STRUCTURES ADD R0, PC ; char * BLX _printf LDR R1, [SP,#0x38+var_34.tm_hour] MOV R0, 0xF2E ; "Hour: %d\n" ADD R0, PC ; char * BLX _printf LDR R1, [SP,#0x38+var_34.tm_min] MOV R0, 0xF28 ; "Minutes: %d\n" ADD R0, PC ; char * BLX _printf LDR R1, [SP,#0x38+var_34] MOV R0, 0xF25 ; "Seconds: %d\n" ADD R0, PC ; char * BLX _printf ADD SP, SP, #0x30 POP {R7,PC} ... 00000000 tm struc ; (sizeof=0x2C, standard type) 00000000 tm_sec DCD ? 00000004 tm_min DCD ? 00000008 tm_hour DCD ? 0000000C tm_mday DCD ? 00000010 tm_mon DCD ? 00000014 tm_year DCD ? 00000018 tm_wday DCD ? 0000001C tm_yday DCD ? 00000020 tm_isdst DCD ? 00000024 tm_gmtoff DCD ? 00000028 tm_zone DCD ? ; offset 0000002C tm ends 18.4 Fields packing in structure One important thing is fields packing in structures4. Let’s take a simple example: #include struct s { char a; int b; char c; int d; }; void f(struct s s) { printf ("a=%d; b=%d; c=%d; d=%d\n", s.a, s.b, s.c, s.d); }; As we see, we have two char fields (each is exactly one byte) and two more —int (each - 4 bytes). 18.4.1 x86 That’s all compiling into: 4See also: Wikipedia: Data structure alignment 161 18.4. FIELDS PACKING IN STRUCTURE CHAPTER 18. STRUCTURES _s$ = 8 ; size = 16 ?f@@YAXUs@@@Z PROC ; f push ebp mov ebp, esp mov eax, DWORD PTR _s$[ebp+12] push eax movsx ecx, BYTE PTR _s$[ebp+8] push ecx mov edx, DWORD PTR _s$[ebp+4] push edx movsx eax, BYTE PTR _s$[ebp] push eax push OFFSET $SG3842 call _printf add esp, 20 pop ebp ret 0 ?f@@YAXUs@@@Z ENDP ; f _TEXT ENDS As we can see, each field’s address is aligned on a 4-bytes border. That’s why each char occupies 4 bytes here (like int). Why? Thus it is easier for CPU to access memory at aligned addresses and to cache data from it. However, it is not very economical in size sense. Let’s try to compile it with option (/Zp1)(/Zp[n] pack structures on n-byte boundary). Listing 18.12: MSVC /Zp1 _TEXT SEGMENT _s$ = 8 ; size = 10 ?f@@YAXUs@@@Z PROC ; f push ebp mov ebp, esp mov eax, DWORD PTR _s$[ebp+6] push eax movsx ecx, BYTE PTR _s$[ebp+5] push ecx mov edx, DWORD PTR _s$[ebp+1] push edx movsx eax, BYTE PTR _s$[ebp] push eax push OFFSET $SG3842 call _printf add esp, 20 pop ebp ret 0 ?f@@YAXUs@@@Z ENDP ; f Now the structure takes only 10 bytes and each char value takes 1 byte. What it give to us? Size economy. And as draw- back —CPU will access these fields without maximal performance it can. As it can be easily guessed, if the structure is used in many source and object files, all these must be compiled with the same convention about structures packing. Aside from MSVC /Zp option which set how to align each structure field, here is also #pragma pack compiler option, it can be defined right in source code. It is available in both MSVC5and GCC6. Let’s back to the SYSTEMTIME structure consisting in 16-bit fields. How our compiler know to pack them on 1-byte align- ment boundary? WinNT.h file has this: Listing 18.13: WinNT.h #include "pshpack1.h" 5MSDN: Working with Packing Structures 6Structure-Packing Pragmas 162 18.4. FIELDS PACKING IN STRUCTURE CHAPTER 18. STRUCTURES And this: Listing 18.14: WinNT.h #include "pshpack4.h" // 4 byte packing is the default The file PshPack1.h looks like: Listing 18.15: PshPack1.h #if ! (defined(lint) || defined(RC_INVOKED)) #if ( _MSC_VER >= 800 && !defined(_M_I86)) || defined(_PUSHPOP_SUPPORTED) #pragma warning(disable:4103) #if !(defined( MIDL_PASS )) || defined( __midl ) #pragma pack(push,1) #else #pragma pack(1) #endif #else #pragma pack(1) #endif #endif /* ! (defined(lint) || defined(RC_INVOKED)) */ That’s how compiler will pack structures defined a er #pragma pack. 18.4.2 ARM + Optimizing Keil + thumb mode Listing 18.16: Optimizing Keil + thumb mode .text:0000003E exit ; CODE XREF: f+16 .text:0000003E 05 B0 ADD SP, SP, #0x14 .text:00000040 00 BD POP {PC} .text:00000280 f .text:00000280 .text:00000280 var_18 = -0x18 .text:00000280 a = -0x14 .text:00000280 b = -0x10 .text:00000280 c = -0xC .text:00000280 d = -8 .text:00000280 .text:00000280 0F B5 PUSH {R0-R3,LR} .text:00000282 81 B0 SUB SP, SP, #4 .text:00000284 04 98 LDR R0, [SP,#16] ; d .text:00000286 02 9A LDR R2, [SP,#8] ; b .text:00000288 00 90 STR R0, [SP] .text:0000028A 68 46 MOV R0, SP .text:0000028C 03 7B LDRB R3, [R0,#12] ; c .text:0000028E 01 79 LDRB R1, [R0,#4] ; a .text:00000290 59 A0 ADR R0, aADBDCDDD ; "a=%d; b=%d; c=%d; d=%d\n" .text:00000292 05 F0 AD FF BL __2printf .text:00000296 D2 E6 B exit As we may recall, here a structure passed instead of pointer to structure, and since first 4 function arguments in ARM are passed via registers, so then structure fields are passed via R0-R3. LDRB loads one byte from memory and extending it to 32-bit, taking into account its sign. This is akin to MOVSX (13.1.1) instruction in x86. Here it is used for loading fields 푎 and 푐 from structure. One more thing we spot easily, instead of function epilogue, here is jump to another function’s epilogue! Indeed, that was quite dierent function, not related in any way to our function, however, it has exactly the same epilogue (probably because, it hold 5 local variables too (5 ∗ 4 = 0푥14)). Also it is located nearly (take a look on addresses). Indeed, there is no dierence, which epilogue to execute, if it works just as we need. Apparently, Keil decides to reuse a part of another function by a reason of economy. Epilogue takes 4 bytes while jump —only 2. 163 18.5. NESTED STRUCTURES CHAPTER 18. STRUCTURES 18.4.3 ARM + Optimizing Xcode (LLVM) + thumb-2 mode Listing 18.17: Optimizing Xcode (LLVM) + thumb-2 mode var_C = -0xC PUSH {R7,LR} MOV R7, SP SUB SP, SP, #4 MOV R9, R1 ; b MOV R1, R0 ; a MOVW R0, #0xF10 ; "a=%d; b=%d; c=%d; d=%d\n" SXTB R1, R1 ; prepare a MOVT.W R0, #0 STR R3, [SP,#0xC+var_C] ; place d to stack for printf() ADD R0, PC ; format-string SXTB R3, R2 ; prepare c MOV R2, R9 ; b BLX _printf ADD SP, SP, #4 POP {R7,PC} SXTB (Signed Extend Byte) is analogous to MOVSX (13.1.1) in x86 as well, but works not with memory, but with register. All the rest —just the same. 18.5 Nested structures Now what about situations when one structure defines another structure inside? #include struct inner_struct { int a; int b; }; struct outer_struct { char a; int b; struct inner_struct c; char d; int e; }; void f(struct outer_struct s) { printf ("a=%d; b=%d; c.a=%d; c.b=%d; d=%d; e=%d\n", s.a, s.b, s.c.a, s.c.b, s.d, s.e); }; ...in this case, both inner_struct fields will be placed between a,b and d,e fields of outer_struct. Let’s compile (MSVC 2010): Listing 18.18: MSVC 2010 _s$ = 8 ; size = 24 _f PROC push ebp mov ebp, esp mov eax, DWORD PTR _s$[ebp+20] ; e push eax 164 18.6. BIT FIELDS IN STRUCTURE CHAPTER 18. STRUCTURES movsx ecx, BYTE PTR _s$[ebp+16] ; d push ecx mov edx, DWORD PTR _s$[ebp+12] ; c.b push edx mov eax, DWORD PTR _s$[ebp+8] ; c.a push eax mov ecx, DWORD PTR _s$[ebp+4] ; b push ecx movsx edx, BYTE PTR _s$[ebp] ;a push edx push OFFSET $SG2466 call _printf add esp, 28 pop ebp ret 0 _f ENDP One curious point here is that by looking onto this assembly code, we do not even see that another structure was used inside of it! Thus, we would say, nested structures are finally unfolds into linear or one-dimensional structure. Of course, if to replace struct inner_struct c; declaration to struct inner_struct *c; (thus making a pointer here) situation will be quite dierent. 18.6 Bit fields in structure 18.6.1 CPUID example C/C++ language allow to define exact number of bits for each structure fields. It is very useful if one needs to save memory space. For example, one bit is enough for variable of bool type. But of course, it is not rational if speed is important. Let’s consider CPUID7instruction example. This instruction returning information about current CPU and its features. If the EAX is set to 1 before instruction execution, CPUID will return this information packed into the EAX register: 3:0 Stepping 7:4 Model 11:8 Family 13:12 Processor Type 19:16 Extended Model 27:20 Extended Family MSVC 2010 has CPUID macro, but GCC 4.4.1 —has not. So let’s make this function by yourself for GCC with the help of its built-in assembler8. #include #ifdef __GNUC__ static inline void cpuid(int code, int *a, int *b, int *c, int *d) { asm volatile("cpuid":"=a"(*a),"=b"(*b),"=c"(*c),"=d"(*d):"a"(code)); } #endif #ifdef _MSC_VER #include #endif struct CPUID_1_EAX { unsigned int stepping:4; unsigned int model:4; unsigned int family_id:4; unsigned int processor_type:2; 7http://en.wikipedia.org/wiki/CPUID 8More about internal GCC assembler 165 18.6. BIT FIELDS IN STRUCTURE CHAPTER 18. STRUCTURES unsigned int reserved1:2; unsigned int extended_model_id:4; unsigned int extended_family_id:8; unsigned int reserved2:4; }; int main() { struct CPUID_1_EAX *tmp; int b[4]; #ifdef _MSC_VER __cpuid(b,1); #endif #ifdef __GNUC__ cpuid (1, &b[0], &b[1], &b[2], &b[3]); #endif tmp=(struct CPUID_1_EAX *)&b[0]; printf ("stepping=%d\n", tmp->stepping); printf ("model=%d\n", tmp->model); printf ("family_id=%d\n", tmp->family_id); printf ("processor_type=%d\n", tmp->processor_type); printf ("extended_model_id=%d\n", tmp->extended_model_id); printf ("extended_family_id=%d\n", tmp->extended_family_id); return 0; }; A er CPUID will fill EAX/EBX/ECX/EDX, these registers will be reflected in the b[] array. Then, we have a pointer to the CPUID_1_EAX structure and we point it to the value in the EAX from b[] array. In other words, we treat 32-bit int value as a structure. Then we read from the stucture. Let’s compile it in MSVC 2008 with /Ox option: Listing 18.19: Optimizing MSVC 2008 _b$ = -16 ; size = 16 _main PROC sub esp, 16 push ebx xor ecx, ecx mov eax, 1 cpuid push esi lea esi, DWORD PTR _b$[esp+24] mov DWORD PTR [esi], eax mov DWORD PTR [esi+4], ebx mov DWORD PTR [esi+8], ecx mov DWORD PTR [esi+12], edx mov esi, DWORD PTR _b$[esp+24] mov eax, esi and eax, 15 push eax push OFFSET $SG15435 ; ’stepping=%d’, 0aH, 00H call _printf mov ecx, esi 166 18.6. BIT FIELDS IN STRUCTURE CHAPTER 18. STRUCTURES shr ecx, 4 and ecx, 15 push ecx push OFFSET $SG15436 ; ’model=%d’, 0aH, 00H call _printf mov edx, esi shr edx, 8 and edx, 15 push edx push OFFSET $SG15437 ; ’family_id=%d’, 0aH, 00H call _printf mov eax, esi shr eax, 12 and eax, 3 push eax push OFFSET $SG15438 ; ’processor_type=%d’, 0aH, 00H call _printf mov ecx, esi shr ecx, 16 and ecx, 15 push ecx push OFFSET $SG15439 ; ’extended_model_id=%d’, 0aH, 00H call _printf shr esi, 20 and esi, 255 push esi push OFFSET $SG15440 ; ’extended_family_id=%d’, 0aH, 00H call _printf add esp, 48 pop esi xor eax, eax pop ebx add esp, 16 ret 0 _main ENDP SHR instruction shi ing value in the EAX register by number of bits must be skipped, e.g., we ignore a bits at right. AND instruction clears bits not needed at le , or, in other words, leaves only those bits in the EAX register we need now. Let’s try GCC 4.4.1 with -O3 option. Listing 18.20: Optimizing GCC 4.4.1 main proc near ; DATA XREF: _start+17 push ebp mov ebp, esp and esp, 0FFFFFFF0h push esi mov esi, 1 push ebx mov eax, esi sub esp, 18h cpuid mov esi, eax and eax, 0Fh mov [esp+8], eax mov dword ptr [esp+4], offset aSteppingD ; "stepping=%d\n" 167 18.6. BIT FIELDS IN STRUCTURE CHAPTER 18. STRUCTURES mov dword ptr [esp], 1 call ___printf_chk mov eax, esi shr eax, 4 and eax, 0Fh mov [esp+8], eax mov dword ptr [esp+4], offset aModelD ; "model=%d\n" mov dword ptr [esp], 1 call ___printf_chk mov eax, esi shr eax, 8 and eax, 0Fh mov [esp+8], eax mov dword ptr [esp+4], offset aFamily_idD ; "family_id=%d\n" mov dword ptr [esp], 1 call ___printf_chk mov eax, esi shr eax, 0Ch and eax, 3 mov [esp+8], eax mov dword ptr [esp+4], offset aProcessor_type ; "processor_type=%d\n" mov dword ptr [esp], 1 call ___printf_chk mov eax, esi shr eax, 10h shr esi, 14h and eax, 0Fh and esi, 0FFh mov [esp+8], eax mov dword ptr [esp+4], offset aExtended_model ; "extended_model_id=%d\n" mov dword ptr [esp], 1 call ___printf_chk mov [esp+8], esi mov dword ptr [esp+4], offset unk_80486D0 mov dword ptr [esp], 1 call ___printf_chk add esp, 18h xor eax, eax pop ebx pop esi mov esp, ebp pop ebp retn main endp Almost the same. The only thing worth noting is the GCC somehow united calculation of extended_model_id and extended_family_id into one block, instead of calculating them separately, before corresponding each printf() call. 18.6.2 Working with the float type as with a structure As it was already noted in section about FPU (15), both float and double types consisted of sign, significand (or fraction) and exponent. But will we able to work with these fields directly? Let’s try with float. 022233031 S exponent mantissa or fraction ( S—sign ) #include #include 168 18.6. BIT FIELDS IN STRUCTURE CHAPTER 18. STRUCTURES #include #include struct float_as_struct { unsigned int fraction : 23; // fractional part unsigned int exponent : 8; // exponent + 0x3FF unsigned int sign : 1; // sign bit }; float f(float _in) { float f=_in; struct float_as_struct t; assert (sizeof (struct float_as_struct) == sizeof (float)); memcpy (&t, &f, sizeof (float)); t.sign=1; // set negative sign t.exponent=t.exponent+2; // multiple d by 2^n (n here is 2) memcpy (&f, &t, sizeof (float)); return f; }; int main() { printf ("%f\n", f(1.234)); }; float_as_struct structure occupies as much space is memory as float, e.g., 4 bytes or 32 bits. Now we setting negative sign in input value and also by adding 2 to exponent we thereby multiplicating the whole number by 22, e.g., by 4. Let’s compile in MSVC 2008 without optimization: Listing 18.21: Non-optimizing MSVC 2008 _t$ = -8 ; size = 4 _f$ = -4 ; size = 4 __in$ = 8 ; size = 4 ?f@@YAMM@Z PROC ; f push ebp mov ebp, esp sub esp, 8 fld DWORD PTR __in$[ebp] fstp DWORD PTR _f$[ebp] push 4 lea eax, DWORD PTR _f$[ebp] push eax lea ecx, DWORD PTR _t$[ebp] push ecx call _memcpy add esp, 12 mov edx, DWORD PTR _t$[ebp] or edx, -2147483648 ; 80000000H - set minus sign mov DWORD PTR _t$[ebp], edx 169 18.6. BIT FIELDS IN STRUCTURE CHAPTER 18. STRUCTURES mov eax, DWORD PTR _t$[ebp] shr eax, 23 ; 00000017H - drop significand and eax, 255 ; 000000ffH - leave here only exponent add eax, 2 ; add 2 to it and eax, 255 ; 000000ffH shl eax, 23 ; 00000017H - shift result to place of bits 30:23 mov ecx, DWORD PTR _t$[ebp] and ecx, -2139095041 ; 807fffffH - drop exponent or ecx, eax ; add original value without exponent with new calculated exponent mov DWORD PTR _t$[ebp], ecx push 4 lea edx, DWORD PTR _t$[ebp] push edx lea eax, DWORD PTR _f$[ebp] push eax call _memcpy add esp, 12 fld DWORD PTR _f$[ebp] mov esp, ebp pop ebp ret 0 ?f@@YAMM@Z ENDP ; f Redundant for a bit. If it is compiled with /Ox flag there is no memcpy() call, f variable is used directly. But it is easier to understand it all considering unoptimized version. What GCC 4.4.1 with -O3 will do? Listing 18.22: Optimizing GCC 4.4.1 ; f(float) public _Z1ff _Z1ff proc near var_4 = dword ptr -4 arg_0 = dword ptr 8 push ebp mov ebp, esp sub esp, 4 mov eax, [ebp+arg_0] or eax, 80000000h ; set minus sign mov edx, eax and eax, 807FFFFFh ; leave only significand and exponent in EAX shr edx, 23 ; prepare exponent add edx, 2 ; add 2 movzx edx, dl ; clear all bits except 7:0 in EAX shl edx, 23 ; shift new calculated exponent to its place or eax, edx ; add new exponent and original value without exponent mov [ebp+var_4], eax fld [ebp+var_4] leave retn _Z1ff endp public main main proc near push ebp mov ebp, esp and esp, 0FFFFFFF0h 170 18.6. BIT FIELDS IN STRUCTURE CHAPTER 18. STRUCTURES sub esp, 10h fld ds:dword_8048614 ; -4.936 fstp qword ptr [esp+8] mov dword ptr [esp+4], offset asc_8048610 ; "%f\n" mov dword ptr [esp], 1 call ___printf_chk xor eax, eax leave retn main endp The f() function is almost understandable. However, what is interesting, GCC was able to calculate f(1.234) result during compilation stage despite all this hodge-podge with structure fields and prepared this argument to the printf() as precalculated! 171 CHAPTER 19. UNIONS Chapter 19 Unions 19.1 Pseudo-random number generator example If we need float random numbers from 0 to 1, the most simplest thing is to use PRNG1 like Mersenne twister produces random 32-bit values in DWORD form, transform this value to float and then dividing it by RAND_MAX (0xFFFFFFFF in our case) —value we got will be in 0..1 interval. But as we know, division operation is slow. Will it be possible to get rid of it, as in case of division by multiplication? (14) Let’s recall what float number consisted of: sign bit, significand bits and exponent bits. We need just to store random bits to all significand bits for getting random float number! Exponent cannot be zero (number will be denormalized in this case), so we will store 01111111 to exponent —this means exponent will be 1. Then fill significand with random bits, set sign bit to 0 (which means positive number) and voilà. Generated numbers will be in 1 to 2 interval, so we also must subtract 1 from it. Very simple linear congruential random numbers generator is used in my example2, produces 32-bit numbers. The PRNG initializing by current time in UNIX-style. Then, float type represented as union —it is the C/C++ construction enabling us to interpret piece of memory as dierently typed. In our case, we are able to create a variable of union type and then access to it as it is float or as it is uint32_t. It can be said, it is just a hack. A dirty one. #include #include #include union uint32_t_float { uint32_t i; float f; }; // from the Numerical Recipes book const uint32_t RNG_a=1664525; const uint32_t RNG_c=1013904223; int main() { uint32_t_float tmp; uint32_t RNG_state=time(NULL); // initial seed for (int i=0; i<100; i++) { RNG_state=RNG_state*RNG_a+RNG_c; tmp.i=RNG_state & 0x007fffff | 0x3F800000; float x=tmp.f-1; printf ("%f\n", x); }; return 0; 1Pseudorandom number generator 2idea was taken from: http://xor0110.wordpress.com/2010/09/24/how-to-generate-floating-point-random-numbers-efficiently 172 19.1. PSEUDO-RANDOM NUMBER GENERATOR EXAMPLE CHAPTER 19. UNIONS }; Listing 19.1: MSVC 2010 (/Ox) $SG4232 DB ’%f’, 0aH, 00H __real@3ff0000000000000 DQ 03ff0000000000000r ; 1 tv140 = -4 ; size = 4 _tmp$ = -4 ; size = 4 _main PROC push ebp mov ebp, esp and esp, -64 ; ffffffc0H sub esp, 56 ; 00000038H push esi push edi push 0 call __time64 add esp, 4 mov esi, eax mov edi, 100 ; 00000064H $LN3@main: ; let’s generate random 32-bit number imul esi, 1664525 ; 0019660dH add esi, 1013904223 ; 3c6ef35fH mov eax, esi ; leave bits for significand only and eax, 8388607 ; 007fffffH ; set exponent to 1 or eax, 1065353216 ; 3f800000H ; store this value as int mov DWORD PTR _tmp$[esp+64], eax sub esp, 8 ; load this value as float fld DWORD PTR _tmp$[esp+72] ; subtract one from it fsub QWORD PTR __real@3ff0000000000000 fstp DWORD PTR tv140[esp+72] fld DWORD PTR tv140[esp+72] fstp QWORD PTR [esp] push OFFSET $SG4232 call _printf add esp, 12 ; 0000000cH dec edi jne SHORT $LN3@main pop edi xor eax, eax 173 19.1. PSEUDO-RANDOM NUMBER GENERATOR EXAMPLE CHAPTER 19. UNIONS pop esi mov esp, ebp pop ebp ret 0 _main ENDP _TEXT ENDS END GCC produces very similar code. 174 CHAPTER 20. POINTERS TO FUNCTIONS Chapter 20 Pointers to functions Pointer to function, as any other pointer, is just an address of function beginning in its code segment. It is o en used in callbacks 1. Well-known examples are: • qsort()2, atexit()3 from the standard C library; • signals in *NIX OS4; • thread starting: CreateThread() (win32), pthread_create() (POSIX); • a lot of win32 functions, e.g. EnumChildWindows()5. So, qsort() function is a C/C++ standard library quicksort implementation. The functions is able to sort anything, any types of data, if you have a function for two elements comparison and qsort() is able to call it. The comparison function can be defined as: int (*compare)(const void *, const void *) Let’s use slightly modified example I found here: 1 /* ex3 Sorting ints with qsort */ 2 3 #include 4 #include 5 6 int comp(const void * _a, const void * _b) 7 { 8 const int *a=(const int *)_a; 9 const int *b=(const int *)_b; 10 11 if (*a==*b) 12 return 0; 13 else 14 if (*a < *b) 15 return -1; 16 else 17 return 1; 18 } 19 20 int main(int argc, char* argv[]) 21 { 22 int numbers[10]={1892,45,200,-98,4087,5,-12345,1087,88,-100000}; 23 int i; 24 1http://en.wikipedia.org/wiki/Callback_(computer_science) 2http://en.wikipedia.org/wiki/Qsort_(C_standard_library) 3http://www.opengroup.org/onlinepubs/009695399/functions/atexit.html 4http://en.wikipedia.org/wiki/Signal.h 5http://msdn.microsoft.com/en-us/library/ms633494(VS.85).aspx 175 20.1. MSVC CHAPTER 20. POINTERS TO FUNCTIONS 25 /* Sort the array */ 26 qsort(numbers,10,sizeof(int),comp) ; 27 for (i=0;i<9;i++) 28 printf("Number = %d\n",numbers[ i ]) ; 29 return 0; 30 } 20.1 MSVC Let’s compile it in MSVC 2010 (I omitted some parts for the sake of brevity) with /Ox option: Listing 20.1: Optimizing MSVC 2010: /Ox /GS- /MD __a$ = 8 ; size = 4 __b$ = 12 ; size = 4 _comp PROC mov eax, DWORD PTR __a$[esp-4] mov ecx, DWORD PTR __b$[esp-4] mov eax, DWORD PTR [eax] mov ecx, DWORD PTR [ecx] cmp eax, ecx jne SHORT $LN4@comp xor eax, eax ret 0 $LN4@comp: xor edx, edx cmp eax, ecx setge dl lea eax, DWORD PTR [edx+edx-1] ret 0 _comp ENDP _numbers$ = -40 ; size = 40 _argc$ = 8 ; size = 4 _argv$ = 12 ; size = 4 _main PROC sub esp, 40 ; 00000028H push esi push OFFSET _comp push 4 lea eax, DWORD PTR _numbers$[esp+52] push 10 ; 0000000aH push eax mov DWORD PTR _numbers$[esp+60], 1892 ; 00000764H mov DWORD PTR _numbers$[esp+64], 45 ; 0000002dH mov DWORD PTR _numbers$[esp+68], 200 ; 000000c8H mov DWORD PTR _numbers$[esp+72], -98 ; ffffff9eH mov DWORD PTR _numbers$[esp+76], 4087 ; 00000ff7H mov DWORD PTR _numbers$[esp+80], 5 mov DWORD PTR _numbers$[esp+84], -12345 ; ffffcfc7H mov DWORD PTR _numbers$[esp+88], 1087 ; 0000043fH mov DWORD PTR _numbers$[esp+92], 88 ; 00000058H mov DWORD PTR _numbers$[esp+96], -100000 ; fffe7960H call _qsort add esp, 16 ; 00000010H ... Nothing surprising so far. As a fourth argument, an address of label _comp is passed, that is just a place where function comp() located. 176 20.1. MSVC CHAPTER 20. POINTERS TO FUNCTIONS How qsort() calling it? Let’s take a look into this function located in MSVCR80.DLL (a MSVC DLL module with C standard library functions): Listing 20.2: MSVCR80.DLL .text:7816CBF0 ; void __cdecl qsort(void *, unsigned int, unsigned int, int (__cdecl *)(const ⤦ Ç void *, const void *)) .text:7816CBF0 public _qsort .text:7816CBF0 _qsort proc near .text:7816CBF0 .text:7816CBF0 lo = dword ptr -104h .text:7816CBF0 hi = dword ptr -100h .text:7816CBF0 var_FC = dword ptr -0FCh .text:7816CBF0 stkptr = dword ptr -0F8h .text:7816CBF0 lostk = dword ptr -0F4h .text:7816CBF0 histk = dword ptr -7Ch .text:7816CBF0 base = dword ptr 4 .text:7816CBF0 num = dword ptr 8 .text:7816CBF0 width = dword ptr 0Ch .text:7816CBF0 comp = dword ptr 10h .text:7816CBF0 .text:7816CBF0 sub esp, 100h .... .text:7816CCE0 loc_7816CCE0: ; CODE XREF: _qsort+B1 .text:7816CCE0 shr eax, 1 .text:7816CCE2 imul eax, ebp .text:7816CCE5 add eax, ebx .text:7816CCE7 mov edi, eax .text:7816CCE9 push edi .text:7816CCEA push ebx .text:7816CCEB call [esp+118h+comp] .text:7816CCF2 add esp, 8 .text:7816CCF5 test eax, eax .text:7816CCF7 jle short loc_7816CD04 comp—is fourth function argument. Here the control is just passed to the address in the comp argument. Before it, two arguments prepared for comp(). Its result is checked a er its execution. That’s why it is dangerous to use pointers to functions. First of all, if you call qsort() with incorrect pointer to function, qsort() may pass control to incorrect point, a process may crash and this bug will be hard to find. Second reason is the callback function types must comply strictly, calling wrong function with wrong arguments of wrong types may lead to serious problems, however, process crashing is not a big problem —big problem is to determine a reason of crashing —because compiler may be silent about potential trouble while compiling. 20.1.1 MSVC + OllyDbg Let’s load our example into OllyDbg and set breakpoint on comp() function. How values are compared we can see at the very first comp() call: fig. 20.1. OllyDbg shows compared values in the window under code window, for convenience. We can also see that theSP pointing to RA where the place in qsort() function is (actually located in MSVCR100.DLL). By tracing (F8) until RETN instruction, and pressing F8 one more time, we returning into qsort() function: fig. 20.2. That was a call to comparison function. Here is also screenshot of the moment of the second call of comp()—now values to be compared are dierent: fig. 20.3. 177 20.1. MSVC CHAPTER 20. POINTERS TO FUNCTIONS Figure 20.1: OllyDbg: first call of comp() Figure 20.2: OllyDbg: the code in qsort() right a er comp() call Figure 20.3: OllyDbg: second call of comp() 20.1.2 MSVC + tracer Let’s also see, which pairs are compared. These 10 numbers are being sorted: 1892, 45, 200, -98, 4087, 5, -12345, 1087, 88, -100000. I found the address of the first CMP instruction in comp(), it is 0x0040100C and I’m setting breakpoint on it: tracer.exe -l:17_1.exe bpx=17_1.exe!0x0040100C I’m getting information about registers at breakpoint: PID=4336|New process 17_1.exe (0) 17_1.exe!0x40100c EAX=0x00000764 EBX=0x0051f7c8 ECX=0x00000005 EDX=0x00000000 ESI=0x0051f7d8 EDI=0x0051f7b4 EBP=0x0051f794 ESP=0x0051f67c 178 20.1. MSVC CHAPTER 20. POINTERS TO FUNCTIONS EIP=0x0028100c FLAGS=IF (0) 17_1.exe!0x40100c EAX=0x00000005 EBX=0x0051f7c8 ECX=0xfffe7960 EDX=0x00000000 ESI=0x0051f7d8 EDI=0x0051f7b4 EBP=0x0051f794 ESP=0x0051f67c EIP=0x0028100c FLAGS=PF ZF IF (0) 17_1.exe!0x40100c EAX=0x00000764 EBX=0x0051f7c8 ECX=0x00000005 EDX=0x00000000 ESI=0x0051f7d8 EDI=0x0051f7b4 EBP=0x0051f794 ESP=0x0051f67c EIP=0x0028100c FLAGS=CF PF ZF IF ... I filtered out EAX and ECX and got: EAX=0x00000764 ECX=0x00000005 EAX=0x00000005 ECX=0xfffe7960 EAX=0x00000764 ECX=0x00000005 EAX=0x0000002d ECX=0x00000005 EAX=0x00000058 ECX=0x00000005 EAX=0x0000043f ECX=0x00000005 EAX=0xffffcfc7 ECX=0x00000005 EAX=0x000000c8 ECX=0x00000005 EAX=0xffffff9e ECX=0x00000005 EAX=0x00000ff7 ECX=0x00000005 EAX=0x00000ff7 ECX=0x00000005 EAX=0xffffff9e ECX=0x00000005 EAX=0xffffff9e ECX=0x00000005 EAX=0xffffcfc7 ECX=0xfffe7960 EAX=0x00000005 ECX=0xffffcfc7 EAX=0xffffff9e ECX=0x00000005 EAX=0xffffcfc7 ECX=0xfffe7960 EAX=0xffffff9e ECX=0xffffcfc7 EAX=0xffffcfc7 ECX=0xfffe7960 EAX=0x000000c8 ECX=0x00000ff7 EAX=0x0000002d ECX=0x00000ff7 EAX=0x0000043f ECX=0x00000ff7 EAX=0x00000058 ECX=0x00000ff7 EAX=0x00000764 ECX=0x00000ff7 EAX=0x000000c8 ECX=0x00000764 EAX=0x0000002d ECX=0x00000764 EAX=0x0000043f ECX=0x00000764 EAX=0x00000058 ECX=0x00000764 EAX=0x000000c8 ECX=0x00000058 EAX=0x0000002d ECX=0x000000c8 EAX=0x0000043f ECX=0x000000c8 EAX=0x000000c8 ECX=0x00000058 EAX=0x0000002d ECX=0x000000c8 EAX=0x0000002d ECX=0x00000058 That’s 34 pairs. Therefore, quick sort algorithm needs 34 comparison operations for sorting these 10 numbers. 20.1.3 MSVC + tracer (code coverage) We can also use tracer’s feature to collect all possible register’s values and show them in IDA. Let’s trace all instructions in comp() function: tracer.exe -l:17_1.exe bpf=17_1.exe!0x00401000,trace:cc We getting .idc-script for loading into IDA and load it: fig. 20.4. IDA gave the function name (PtFuncCompare) —it seems, because IDA sees that pointer to this function is passed into qsort(). 179 20.2. GCC CHAPTER 20. POINTERS TO FUNCTIONS We see that 푎 and 푏 pointers are points to various places in array, but step between points is 4—indeed, 32-bit values are stored in the array. We see that the instructions at 0x401010 and 0x401012 was never executed (so they leaved as white): indeed, comp() was never returned 0, because there no equal elements. Figure 20.4: tracer and IDA. N.B.: some values are cutted at right 20.2 GCC Not a big dierence: Listing 20.3: GCC lea eax, [esp+40h+var_28] mov [esp+40h+var_40], eax mov [esp+40h+var_28], 764h mov [esp+40h+var_24], 2Dh mov [esp+40h+var_20], 0C8h mov [esp+40h+var_1C], 0FFFFFF9Eh mov [esp+40h+var_18], 0FF7h mov [esp+40h+var_14], 5 mov [esp+40h+var_10], 0FFFFCFC7h mov [esp+40h+var_C], 43Fh mov [esp+40h+var_8], 58h mov [esp+40h+var_4], 0FFFE7960h mov [esp+40h+var_34], offset comp mov [esp+40h+var_38], 4 mov [esp+40h+var_3C], 0Ah call _qsort comp() function: public comp comp proc near arg_0 = dword ptr 8 arg_4 = dword ptr 0Ch push ebp 180 20.2. GCC CHAPTER 20. POINTERS TO FUNCTIONS mov ebp, esp mov eax, [ebp+arg_4] mov ecx, [ebp+arg_0] mov edx, [eax] xor eax, eax cmp [ecx], edx jnz short loc_8048458 pop ebp retn loc_8048458: setnl al movzx eax, al lea eax, [eax+eax-1] pop ebp retn comp endp qsort() implementation is located in the libc.so.6 and it is in fact just a wrapper 6 for qsort_r(). It will call then quicksort(), where our defined function will be called via passed pointer: Listing 20.4: (file libc.so.6, glibc version—2.10.1) .text:0002DDF6 mov edx, [ebp+arg_10] .text:0002DDF9 mov [esp+4], esi .text:0002DDFD mov [esp], edi .text:0002DE00 mov [esp+8], edx .text:0002DE04 call [ebp+arg_C] ... 20.2.1 GCC + GDB (with source code) Obviously, we have a C-source code of our example (20), so we can set breakpoint (b) on line number (11th—the line where first comparison is occurred). We also need to compile example with debugging information included (-g), so the table with addresses and corresponding line numbers is present. We can also print values by variable name (p): debugging information also has information about which register and/or local stack element contain which variable. We can also see stack (bt) and find out that there are some intermediate function msort_with_tmp() used in Glibc. Listing 20.5: GDB session dennis@ubuntuvm:~/polygon$ gcc 17_1.c -g dennis@ubuntuvm:~/polygon$ gdb ./a.out GNU gdb (GDB) 7.6.1-ubuntu Copyright (C) 2013 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Type "show copying" and "show warranty" for details. This GDB was configured as "i686-linux-gnu". For bug reporting instructions, please see: ) at msort.c:307 #9 0x0804850d in main (argc=1, argv=0xbffff1c4) at 17_1.c:26 (gdb) 20.2.2 GCC + GDB (no source code) But o en there are no source code at all, so we can disassemble comp() function (disas), find the very first CMP instruction and set breakpoint (b) at that address. At each breakpoint, we will dump all register contents (info registers). Stack information is also available (bt), but partial: there are no line number information for comp() function. Listing 20.6: GDB session dennis@ubuntuvm:~/polygon$ gcc 17_1.c dennis@ubuntuvm:~/polygon$ gdb ./a.out GNU gdb (GDB) 7.6.1-ubuntu Copyright (C) 2013 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Type "show copying" and "show warranty" for details. This GDB was configured as "i686-linux-gnu". For bug reporting instructions, please see: 0x0804846d <+32>: mov eax,0x0 0x08048472 <+37>: jmp 0x804848e 0x08048474 <+39>: mov eax,DWORD PTR [ebp-0x8] 0x08048477 <+42>: mov edx,DWORD PTR [eax] 0x08048479 <+44>: mov eax,DWORD PTR [ebp-0x4] 0x0804847c <+47>: mov eax,DWORD PTR [eax] 0x0804847e <+49>: cmp edx,eax 0x08048480 <+51>: jge 0x8048489 0x08048482 <+53>: mov eax,0xffffffff 0x08048487 <+58>: jmp 0x804848e 0x08048489 <+60>: mov eax,0x1 0x0804848e <+65>: leave 0x0804848f <+66>: ret End of assembler dump. (gdb) b *0x08048469 Breakpoint 1 at 0x8048469 (gdb) run Starting program: /home/dennis/polygon/./a.out Breakpoint 1, 0x08048469 in comp () (gdb) info registers eax 0x2d 45 ecx 0xbffff0f8 -1073745672 edx 0x764 1892 ebx 0xb7fc0000 -1208221696 esp 0xbfffeeb8 0xbfffeeb8 ebp 0xbfffeec8 0xbfffeec8 esi 0xbffff0fc -1073745668 edi 0xbffff010 -1073745904 eip 0x8048469 0x8048469 eflags 0x286 [ PF SF IF ] cs 0x73 115 ss 0x7b 123 ds 0x7b 123 es 0x7b 123 fs 0x0 0 gs 0x33 51 (gdb) c Continuing. Breakpoint 1, 0x08048469 in comp () (gdb) info registers eax 0xff7 4087 ecx 0xbffff104 -1073745660 edx 0xffffff9e -98 ebx 0xb7fc0000 -1208221696 esp 0xbfffee58 0xbfffee58 ebp 0xbfffee68 0xbfffee68 esi 0xbffff108 -1073745656 edi 0xbffff010 -1073745904 eip 0x8048469 0x8048469 eflags 0x282 [ SF IF ] cs 0x73 115 ss 0x7b 123 ds 0x7b 123 es 0x7b 123 fs 0x0 0 gs 0x33 51 (gdb) c 183 20.2. GCC CHAPTER 20. POINTERS TO FUNCTIONS Continuing. Breakpoint 1, 0x08048469 in comp () (gdb) info registers eax 0xffffff9e -98 ecx 0xbffff100 -1073745664 edx 0xc8 200 ebx 0xb7fc0000 -1208221696 esp 0xbfffeeb8 0xbfffeeb8 ebp 0xbfffeec8 0xbfffeec8 esi 0xbffff104 -1073745660 edi 0xbffff010 -1073745904 eip 0x8048469 0x8048469 eflags 0x286 [ PF SF IF ] cs 0x73 115 ss 0x7b 123 ds 0x7b 123 es 0x7b 123 fs 0x0 0 gs 0x33 51 (gdb) bt #0 0x08048469 in comp () #1 0xb7e42872 in msort_with_tmp (p=p@entry=0xbffff07c, b=b@entry=0xbffff0f8, n=n@entry=2) at msort.c:65 #2 0xb7e4273e in msort_with_tmp (n=2, b=0xbffff0f8, p=0xbffff07c) at msort.c:45 #3 msort_with_tmp (p=p@entry=0xbffff07c, b=b@entry=0xbffff0f8, n=n@entry=5) at msort.c:53 #4 0xb7e4273e in msort_with_tmp (n=5, b=0xbffff0f8, p=0xbffff07c) at msort.c:45 #5 msort_with_tmp (p=p@entry=0xbffff07c, b=b@entry=0xbffff0f8, n=n@entry=10) at msort.c:53 #6 0xb7e42cef in msort_with_tmp (n=10, b=0xbffff0f8, p=0xbffff07c) at msort.c:45 #7 __GI_qsort_r (b=b@entry=0xbffff0f8, n=n@entry=10, s=s@entry=4, cmp=cmp@entry=0x804844d <⤦ Ç comp>, arg=arg@entry=0x0) at msort.c:297 #8 0xb7e42dcf in __GI_qsort (b=0xbffff0f8, n=10, s=4, cmp=0x804844d ) at msort.c:307 #9 0x0804850d in main () 184 CHAPTER 21. 64-BIT VALUES IN 32-BIT ENVIRONMENT Chapter 21 64-bit values in 32-bit environment In the 32-bit environment GPR’s are 32-bit, so 64-bit values are passed as 32-bit value pairs 1. 21.1 Arguments passing, addition, subtraction #include uint64_t f1 (uint64_t a, uint64_t b) { return a+b; }; void f1_test () { #ifdef __GNUC__ printf ("%lld\n", f1(12345678901234, 23456789012345)); #else printf ("%I64d\n", f1(12345678901234, 23456789012345)); #endif }; uint64_t f2 (uint64_t a, uint64_t b) { return a-b; }; Listing 21.1: MSVC 2012 /Ox /Ob1 _a$ = 8 ; size = 8 _b$ = 16 ; size = 8 _f1 PROC mov eax, DWORD PTR _a$[esp-4] add eax, DWORD PTR _b$[esp-4] mov edx, DWORD PTR _a$[esp] adc edx, DWORD PTR _b$[esp] ret 0 _f1 ENDP _f1_test PROC push 5461 ; 00001555H push 1972608889 ; 75939f79H push 2874 ; 00000b3aH push 1942892530 ; 73ce2ff2H call _f1 push edx 1By the way, 32-bit values are passed as pairs in 16-bit environment just as the same 185 21.2. MULTIPLICATION, DIVISION CHAPTER 21. 64-BIT VALUES IN 32-BIT ENVIRONMENT push eax push OFFSET $SG1436 ; ’%I64d’, 0aH, 00H call _printf add esp, 28 ret 0 _f1_test ENDP _f2 PROC mov eax, DWORD PTR _a$[esp-4] sub eax, DWORD PTR _b$[esp-4] mov edx, DWORD PTR _a$[esp] sbb edx, DWORD PTR _b$[esp] ret 0 _f2 ENDP We may see in the f1_test() function as each 64-bit value is passed by two 32-bit values, high part first, then low part. Addition and subtraction occurring by pairs as well. While addition, low 32-bit part are added first. If carry was occurred while addition, CF flag is set. The next ADC instruc- tion adds high parts of values, but also adding 1 if CF=1. Subtraction is also occurred by pairs. The very first SUB may also turn CF flag on, which will be checked in the subsequent SBB instruction: if carry flag is on, then 1 will also be subtracted from the result. In a 32-bit environment, 64-bit values are returned from a functions in EDX:EAX registers pair. It is easily can be seen how f1() function is then passed to printf(). Listing 21.2: GCC 4.8.1 -O1 -fno-inline _f1: mov eax, DWORD PTR [esp+12] mov edx, DWORD PTR [esp+16] add eax, DWORD PTR [esp+4] adc edx, DWORD PTR [esp+8] ret _f1_test: sub esp, 28 mov DWORD PTR [esp+8], 1972608889 ; 75939f79H mov DWORD PTR [esp+12], 5461 ; 00001555H mov DWORD PTR [esp], 1942892530 ; 73ce2ff2H mov DWORD PTR [esp+4], 2874 ; 00000b3aH call _f1 mov DWORD PTR [esp+4], eax mov DWORD PTR [esp+8], edx mov DWORD PTR [esp], OFFSET FLAT:LC0 ; "%lld\12\0" call _printf add esp, 28 ret _f2: mov eax, DWORD PTR [esp+4] mov edx, DWORD PTR [esp+8] sub eax, DWORD PTR [esp+12] sbb edx, DWORD PTR [esp+16] ret GCC code is the same. 21.2 Multiplication, division 186 21.2. MULTIPLICATION, DIVISION CHAPTER 21. 64-BIT VALUES IN 32-BIT ENVIRONMENT #include uint64_t f3 (uint64_t a, uint64_t b) { return a*b; }; uint64_t f4 (uint64_t a, uint64_t b) { return a/b; }; uint64_t f5 (uint64_t a, uint64_t b) { return a % b; }; Listing 21.3: MSVC 2012 /Ox /Ob1 _a$ = 8 ; size = 8 _b$ = 16 ; size = 8 _f3 PROC push DWORD PTR _b$[esp] push DWORD PTR _b$[esp] push DWORD PTR _a$[esp+8] push DWORD PTR _a$[esp+8] call __allmul ; long long multiplication ret 0 _f3 ENDP _a$ = 8 ; size = 8 _b$ = 16 ; size = 8 _f4 PROC push DWORD PTR _b$[esp] push DWORD PTR _b$[esp] push DWORD PTR _a$[esp+8] push DWORD PTR _a$[esp+8] call __aulldiv ; unsigned long long division ret 0 _f4 ENDP _a$ = 8 ; size = 8 _b$ = 16 ; size = 8 _f5 PROC push DWORD PTR _b$[esp] push DWORD PTR _b$[esp] push DWORD PTR _a$[esp+8] push DWORD PTR _a$[esp+8] call __aullrem ; unsigned long long remainder ret 0 _f5 ENDP Multiplication and division is more complex operation, so usually, the compiler embedds calls to the library functions doing that. These functions meaning are here:E. Listing 21.4: GCC 4.8.1 -O3 -fno-inline _f3: push ebx mov edx, DWORD PTR [esp+8] 187 21.3. SHIFTING RIGHT CHAPTER 21. 64-BIT VALUES IN 32-BIT ENVIRONMENT mov eax, DWORD PTR [esp+16] mov ebx, DWORD PTR [esp+12] mov ecx, DWORD PTR [esp+20] imul ebx, eax imul ecx, edx mul edx add ecx, ebx add edx, ecx pop ebx ret _f4: sub esp, 28 mov eax, DWORD PTR [esp+40] mov edx, DWORD PTR [esp+44] mov DWORD PTR [esp+8], eax mov eax, DWORD PTR [esp+32] mov DWORD PTR [esp+12], edx mov edx, DWORD PTR [esp+36] mov DWORD PTR [esp], eax mov DWORD PTR [esp+4], edx call ___udivdi3 ; unsigned division add esp, 28 ret _f5: sub esp, 28 mov eax, DWORD PTR [esp+40] mov edx, DWORD PTR [esp+44] mov DWORD PTR [esp+8], eax mov eax, DWORD PTR [esp+32] mov DWORD PTR [esp+12], edx mov edx, DWORD PTR [esp+36] mov DWORD PTR [esp], eax mov DWORD PTR [esp+4], edx call ___umoddi3 ; unsigned modulo add esp, 28 ret GCC doing almost the same, but multiplication code is inlined right in the function, thinking it could be more eicient. GCC has dierent library function names:D. 21.3 Shi ing right #include uint64_t f6 (uint64_t a) { return a>>7; }; Listing 21.5: MSVC 2012 /Ox /Ob1 _a$ = 8 ; size = 8 _f6 PROC mov eax, DWORD PTR _a$[esp-4] mov edx, DWORD PTR _a$[esp] shrd eax, edx, 7 shr edx, 7 ret 0 188 21.4. CONVERTING OF 32-BIT VALUE INTO 64-BIT ONE CHAPTER 21. 64-BIT VALUES IN 32-BIT ENVIRONMENT _f6 ENDP Listing 21.6: GCC 4.8.1 -O3 -fno-inline _f6: mov edx, DWORD PTR [esp+8] mov eax, DWORD PTR [esp+4] shrd eax, edx, 7 shr edx, 7 ret Shi ing also occurring in two passes: first lower part is shi ing, then higher part. But the lower part is shi ing with the help of SHRD instruction, it shi ing EDX value by 7 bits, but pulling new bits from EAX, i.e., from the higher part. Higher part is shi ing using more popular SHR instruction: indeed, freed bits in the higher part should be just filled with zeroes. 21.4 Converting of 32-bit value into 64-bit one #include int64_t f7 (int64_t a, int64_t b, int32_t c) { return a*b+c; }; int64_t f7_main () { return f7(12345678901234, 23456789012345, 12345); }; Listing 21.7: MSVC 2012 /Ox /Ob1 _a$ = 8 ; size = 8 _b$ = 16 ; size = 8 _c$ = 24 ; size = 4 _f7 PROC push esi push DWORD PTR _b$[esp+4] push DWORD PTR _b$[esp+4] push DWORD PTR _a$[esp+12] push DWORD PTR _a$[esp+12] call __allmul ; long long multiplication mov ecx, eax mov eax, DWORD PTR _c$[esp] mov esi, edx cdq ; input: 32-bit value in EAX; output: 64-bit value in EDX:EAX add eax, ecx adc edx, esi pop esi ret 0 _f7 ENDP _f7_main PROC push 12345 ; 00003039H push 5461 ; 00001555H push 1972608889 ; 75939f79H push 2874 ; 00000b3aH push 1942892530 ; 73ce2ff2H call _f7 add esp, 20 ; 00000014H ret 0 _f7_main ENDP 189 21.4. CONVERTING OF 32-BIT VALUE INTO 64-BIT ONE CHAPTER 21. 64-BIT VALUES IN 32-BIT ENVIRONMENT Here we also run into necessity to extend 32-bit signed value from 푐 into 64-bit signed. Unsigned values are converted straightforwardly: all bits in higher part should be set to 0. But it is not appropriate for signed data types: sign should be copied into higher part of resulting number. An instruction CDQ doing that here, it takes input value in EAX, extending value to 64-bit and leaving it in the EDX:EAX registers pair. In other words, CDQ instruction getting number sign in EAX (by getting just most significant bit in EAX), and depending of it, setting all 32-bits in EDX to 0 or 1. Its operation is somewhat similar to the MOVSX (13.1.1) instruction. Listing 21.8: GCC 4.8.1 -O3 -fno-inline _f7: push edi push esi push ebx mov esi, DWORD PTR [esp+16] mov edi, DWORD PTR [esp+24] mov ebx, DWORD PTR [esp+20] mov ecx, DWORD PTR [esp+28] mov eax, esi mul edi imul ebx, edi imul ecx, esi mov esi, edx add ecx, ebx mov ebx, eax mov eax, DWORD PTR [esp+32] add esi, ecx cdq ; input: 32-bit value in EAX; output: 64-bit value in EDX:EAX add eax, ebx adc edx, esi pop ebx pop esi pop edi ret _f7_main: sub esp, 28 mov DWORD PTR [esp+16], 12345 ; 00003039H mov DWORD PTR [esp+8], 1972608889 ; 75939f79H mov DWORD PTR [esp+12], 5461 ; 00001555H mov DWORD PTR [esp], 1942892530 ; 73ce2ff2H mov DWORD PTR [esp+4], 2874 ; 00000b3aH call _f7 add esp, 28 ret GCC generates just the same code as MSVC, but inlines multiplication code right in the function. See also: 32-bit values in 16-bit environment: 31.4. 190 CHAPTER 22. SIMD Chapter 22 SIMD SIMD1 is just acronym: Single Instruction, Multiple Data. As it is said, it is multiple data processing using only one instruction. Just as FPU, that CPU subsystem looks like separate processor inside x86. SIMD began as MMX in x86. 8 new 64-bit registers appeared: MM0-MM7. Each MMX register may hold 2 32-bit values, 4 16-bit values or 8 bytes. For example, it is possible to add 8 8-bit values (bytes) simultaneously by adding two values in MMX-registers. One simple example is graphics editor, representing image as a two dimensional array. When user change image bright- ness, the editor must add a coeicient to each pixel value, or to subtract. For the sake of brevity, our image may be grayscale and each pixel defined by one 8-bit byte, then it is possible to change brightness of 8 pixels simultaneously. When MMX appeared, these registers was actually located in FPU registers. It was possible to use either FPU or MMX at the same time. One might think, Intel saved on transistors, but in fact, the reason of such symbiosis is simpler —olderOS may not aware of additional CPU registers would not save them at the context switching, but will save FPU registers. Thus, MMX-enabled CPU + oldOS + process utilizing MMX features = that all will work together. SSE—is extension of SIMD registers up to 128 bits, now separately from FPU. AVX—another extension to 256 bits. Now about practical usage. Of course, memory copying (memcpy), memory comparing (memcmp) and so on. One more example: we got DES encryption algorithm, it takes 64-bit block, 56-bit key, encrypt block and produce 64-bit result. DES algorithm may be considered as a very large electronic circuit, with wires and AND/OR/NOT gates. Bitslice DES2 —is an idea of processing group of blocks and keys simultaneously. Let’s say, variable of type unsigned int on x86 may hold up to 32 bits, so, it is possible to store there intermediate results for 32 blocks-keys pairs simultaneously, using 64+56 variables of unsigned int type. I wrote an utility to brute-force Oracle RDBMS passwords/hashes (ones based on DES), slightly modified bitslice DES al- gorithm for SSE2 and AVX —now it is possible to encrypt 128 or 256 block-keys pairs simultaneously. http://conus.info/utils/ops_SIMD/ 22.1 Vectorization Vectorization3, for example, is when you have a loop taking couple of arrays at input and produces one array. Loop body takes values from input arrays, do something and put result into output array. It is important that there is only one single operation applied to each element. Vectorization —is to process several elements simultaneously. Vectorization is not very fresh technology: author of this textbook saw it at least on Cray Y-MP supercomputer line from 1988 when played with its “lite” version Cray Y-MP EL 4. For example: for (i = 0; i < 1024; i++) { C[i] = A[i]*B[i]; } This fragment of code takes elements from A and B, multiplies them and save result into C. 1Single instruction, multiple data 2http://www.darkside.com.au/bitslice/ 3Wikipedia: vectorization 4Remotely. It is installed in the museum of supercomputers: http://www.cray-cyber.org 191 22.1. VECTORIZATION CHAPTER 22. SIMD If each array element we have is 32-bit int, then it is possible to load 4 elements from A into 128-bit XMM-register, from B to another XMM-registers, and by executing PMULLD (Multiply Packed Signed Dword Integers and Store Low Result) and PMULHW (Multiply Packed Signed Integers and Store High Result), it is possible to get 4 64-bit products at once. Thus, loop body count is 1024⇑4 instead of 1024, that is 4 times less and, of course, faster. Some compilers can do vectorization automatically in a simple cases, e.g., Intel C++5. I wrote tiny function: int f (int sz, int *ar1, int *ar2, int *ar3) { for (int i=0; i #include int main () { printf ("32.01 ^ 1.54 = %lf\n", pow (32.01,1.54)); return 0; } They are passed in lower halves of the XMM0-XMM3 registers. Listing 24.3: MSVC 2012 x64 /Ox $SG1354 DB ’32.01 ^ 1.54 = %lf’, 0aH, 00H __real@40400147ae147ae1 DQ 040400147ae147ae1r ; 32.01 __real@3ff8a3d70a3d70a4 DQ 03ff8a3d70a3d70a4r ; 1.54 main PROC sub rsp, 40 ; 00000028H movsdx xmm1, QWORD PTR __real@3ff8a3d70a3d70a4 movsdx xmm0, QWORD PTR __real@40400147ae147ae1 call pow lea rcx, OFFSET FLAT:$SG1354 movaps xmm1, xmm0 movd rdx, xmm1 call printf xor eax, eax add rsp, 40 ; 00000028H ret 0 main ENDP There are noMOVSDXinstruction in Intel [14] and AMD [1] manuals, it is called there justMOVSD. So there are two instructions sharing the same name in x86 (about other: B.6.2). Apparently, Microso developers wanted to get rid of mess, so they renamed it into MOVSDX. It just loads a value into lower half of XMM-register. pow() takes arguments from XMM0 and XMM1, and returning result in XMM0. It is then moved into RDX for printf(). Why? Honestly speaking, I don’t know, maybe because printf()—is a variable arguments function? 210 24.3. COMPARISON EXAMPLE CHAPTER 24. WORKING WITH FLOAT POINT NUMBERS USING SIMD IN X64 Listing 24.4: GCC 4.4.6 x64 -O3 .LC2: .string "32.01 ^ 1.54 = %lf\n" main: sub rsp, 8 movsd xmm1, QWORD PTR .LC0[rip] movsd xmm0, QWORD PTR .LC1[rip] call pow ; result is now in XMM0 mov edi, OFFSET FLAT:.LC2 mov eax, 1 ; number of vector registers passed call printf xor eax, eax add rsp, 8 ret .LC0: .long 171798692 .long 1073259479 .LC1: .long 2920577761 .long 1077936455 GCC making more clear result. Value for printf() is passed in XMM0. By the way, here is a case when 1 is written into EAX for printf()—this mean that one argument will be passed in vector registers, just as the standard requires [21]. 24.3 Comparison example double d_max (double a, double b) { if (a>b) return a; return b; }; Listing 24.5: MSVC 2012 x64 /Ox a$ = 8 b$ = 16 d_max PROC comisd xmm0, xmm1 ja SHORT $LN2@d_max movaps xmm0, xmm1 $LN2@d_max: fatret 0 d_max ENDP Optimizing MSVC generates very easy code to understand. COMISD is “Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS”. Essentially, that is what it does. Non-optimizing MSVC generates more redundant code, but it is still not hard to understand: Listing 24.6: MSVC 2012 x64 a$ = 8 b$ = 16 d_max PROC movsdx QWORD PTR [rsp+16], xmm1 movsdx QWORD PTR [rsp+8], xmm0 movsdx xmm0, QWORD PTR a$[rsp] 211 24.4. SUMMARY CHAPTER 24. WORKING WITH FLOAT POINT NUMBERS USING SIMD IN X64 comisd xmm0, QWORD PTR b$[rsp] jbe SHORT $LN1@d_max movsdx xmm0, QWORD PTR a$[rsp] jmp SHORT $LN2@d_max $LN1@d_max: movsdx xmm0, QWORD PTR b$[rsp] $LN2@d_max: fatret 0 d_max ENDP However, GCC 4.4.6 did more optimizing and used the MAXSD (“Return Maximum Scalar Double-Precision Floating-Point Value”) instruction, which just choose maximal value! Listing 24.7: GCC 4.4.6 x64 -O3 d_max: maxsd xmm0, xmm1 ret 24.4 Summary Only lower half of XMM-registers are used in all examples here, a number in IEEE 754 format is stored there. Essentially, all instructions prefixed by -SD (“Scalar Double-Precision”)—are instructions working with float point num- bers in IEEE 754 format stored in the lower 64-bit half of XMM-register. And it is easier than FPU, apparently because SIMD extensions were evolved not as chaotic as FPU in the past. Stack register model is not used. If you would try to replace double to float in these examples, the same instructions will be used, but prefixed with -SS (“Scalar Single-Precision”), for example, MOVSS, COMISS, ADDSS, etc. “Scalar” mean that SIMD-register will contain only one value instead of several. Instructions working with several values in a register simultaneously, has “Packed” in the name. 212 CHAPTER 25. TEMPERATURE CONVERTING Chapter 25 Temperature converting Another very popular example in programming books for beginners, is a small program converting Fahrenheit temperature to Celsius or back. 퐶 = 5 ⋅ (퐹 − 32) 9 I also added simple error handling: 1) we should check if user enters correct number; 2) we should check if Celsius tem- perature is not below −273 number (which is below absolute zero, as we may remember from school physics lessons). exit() function terminates program instantly, without returning to the caller function. 25.1 Integer values #include #include int main() { int celsius, fahr; printf ("Enter temperature in Fahrenheit:\n"); if (scanf ("%d", &fahr)!=1) { printf ("Error while parsing your input\n"); exit(0); }; celsius = 5 * (fahr-32) / 9; if (celsius<-273) { printf ("Error: incorrect temperature!\n"); exit(0); }; printf ("Celsius: %d\n", celsius); }; 25.1.1 MSVC 2012 x86 /Ox Listing 25.1: MSVC 2012 x86 /Ox $SG4228 DB ’Enter temperature in Fahrenheit:’, 0aH, 00H $SG4230 DB ’%d’, 00H $SG4231 DB ’Error while parsing your input’, 0aH, 00H $SG4233 DB ’Error: incorrect temperature!’, 0aH, 00H $SG4234 DB ’Celsius: %d’, 0aH, 00H 213 25.1. INTEGER VALUES CHAPTER 25. TEMPERATURE CONVERTING _fahr$ = -4 ; size = 4 _main PROC push ecx push esi mov esi, DWORD PTR __imp__printf push OFFSET $SG4228 ; ’Enter temperature in Fahrenheit:’ call esi ; call printf() lea eax, DWORD PTR _fahr$[esp+12] push eax push OFFSET $SG4230 ; ’%d’ call DWORD PTR __imp__scanf add esp, 12 ; 0000000cH cmp eax, 1 je SHORT $LN2@main push OFFSET $SG4231 ; ’Error while parsing your input’ call esi ; call printf() add esp, 4 push 0 call DWORD PTR __imp__exit $LN9@main: $LN2@main: mov eax, DWORD PTR _fahr$[esp+8] add eax, -32 ; ffffffe0H lea ecx, DWORD PTR [eax+eax*4] mov eax, 954437177 ; 38e38e39H imul ecx sar edx, 1 mov eax, edx shr eax, 31 ; 0000001fH add eax, edx cmp eax, -273 ; fffffeefH jge SHORT $LN1@main push OFFSET $SG4233 ; ’Error: incorrect temperature!’ call esi ; call printf() add esp, 4 push 0 call DWORD PTR __imp__exit $LN10@main: $LN1@main: push eax push OFFSET $SG4234 ; ’Celsius: %d’ call esi ; call printf() add esp, 8 ; return 0 - at least by C99 standard xor eax, eax pop esi pop ecx ret 0 $LN8@main: _main ENDP What we can say about it: • Address of printf() is first loaded into ESI register, so the subsequent printf() calls are processed just by CALL ESI instruction. It’s a very popular compiler technique, possible if several consequent calls to the same function are present in the code, and/or, if there are free register which can be used for this. • We see ADD EAX, -32 instruction at the place where 32 should be subtracted from the value. 퐸퐴푋 = 퐸퐴푋 + (−32) is equivalent to 퐸퐴푋 = 퐸퐴푋 − 32 and somehow, compiler decide to use ADD instead of SUB. Maybe it’s worth it. • LEA instruction is used when value should be multiplied by 5: lea ecx, DWORD PTR [eax+eax*4]. Yes, 푖 + 푖 ∗ 4 is equivalent to 푖 ∗ 5 and LEA works faster then IMUL. By the way, SHL EAX, 2 / ADD EAX, EAX instructions pair could be also used here instead— some compilers do it in this way. 214 25.2. FLOAT POINT VALUES CHAPTER 25. TEMPERATURE CONVERTING • Division by multiplication trick (14) is also used here. • main() function returns 0 while we haven’t return 0 at its end. C99 standard tells us [15, 5.1.2.2.3] that main() will return 0 in case of return statement absence. This rule works only for main() function. Though, MSVC doesn’t support C99, but maybe partly it does? 25.1.2 MSVC 2012 x64 /Ox The code is almost the same, but I’ve found INT 3 instructions a er each exit() call: xor ecx, ecx call QWORD PTR __imp_exit int 3 INT 3 is a debugger breakpoint. It is known that exit() is one of functions which never can return 1, so if it does, something really odd happens and it’s time to load debugger. 25.2 Float point values #include #include int main() { double celsius, fahr; printf ("Enter temperature in Fahrenheit:\n"); if (scanf ("%lf", &fahr)!=1) { printf ("Error while parsing your input\n"); exit(0); }; celsius = 5 * (fahr-32) / 9; if (celsius<-273) { printf ("Error: incorrect temperature!\n"); exit(0); }; printf ("Celsius: %lf\n", celsius); }; MSVC 2010 x86 use FPU instructions... Listing 25.2: MSVC 2010 x86 /Ox $SG4038 DB ’Enter temperature in Fahrenheit:’, 0aH, 00H $SG4040 DB ’%lf’, 00H $SG4041 DB ’Error while parsing your input’, 0aH, 00H $SG4043 DB ’Error: incorrect temperature!’, 0aH, 00H $SG4044 DB ’Celsius: %lf’, 0aH, 00H __real@c071100000000000 DQ 0c071100000000000r ; -273 __real@4022000000000000 DQ 04022000000000000r ; 9 __real@4014000000000000 DQ 04014000000000000r ; 5 __real@4040000000000000 DQ 04040000000000000r ; 32 _fahr$ = -8 ; size = 8 _main PROC 1another popular one is longjmp() 215 25.2. FLOAT POINT VALUES CHAPTER 25. TEMPERATURE CONVERTING sub esp, 8 push esi mov esi, DWORD PTR __imp__printf push OFFSET $SG4038 ; ’Enter temperature in Fahrenheit:’ call esi ; call printf lea eax, DWORD PTR _fahr$[esp+16] push eax push OFFSET $SG4040 ; ’%lf’ call DWORD PTR __imp__scanf add esp, 12 ; 0000000cH cmp eax, 1 je SHORT $LN2@main push OFFSET $SG4041 ; ’Error while parsing your input’ call esi ; call printf add esp, 4 push 0 call DWORD PTR __imp__exit $LN2@main: fld QWORD PTR _fahr$[esp+12] fsub QWORD PTR __real@4040000000000000 ; 32 fmul QWORD PTR __real@4014000000000000 ; 5 fdiv QWORD PTR __real@4022000000000000 ; 9 fld QWORD PTR __real@c071100000000000 ; -273 fcomp ST(1) fnstsw ax test ah, 65 ; 00000041H jne SHORT $LN1@main push OFFSET $SG4043 ; ’Error: incorrect temperature!’ fstp ST(0) call esi ; call printf add esp, 4 push 0 call DWORD PTR __imp__exit $LN1@main: sub esp, 8 fstp QWORD PTR [esp] push OFFSET $SG4044 ; ’Celsius: %lf’ call esi add esp, 12 ; 0000000cH ; return 0 xor eax, eax pop esi add esp, 8 ret 0 $LN10@main: _main ENDP ... but MSVC from year 2012 use SIMD instructions instead: Listing 25.3: MSVC 2010 x86 /Ox $SG4228 DB ’Enter temperature in Fahrenheit:’, 0aH, 00H $SG4230 DB ’%lf’, 00H $SG4231 DB ’Error while parsing your input’, 0aH, 00H $SG4233 DB ’Error: incorrect temperature!’, 0aH, 00H $SG4234 DB ’Celsius: %lf’, 0aH, 00H __real@c071100000000000 DQ 0c071100000000000r ; -273 __real@4040000000000000 DQ 04040000000000000r ; 32 __real@4022000000000000 DQ 04022000000000000r ; 9 __real@4014000000000000 DQ 04014000000000000r ; 5 _fahr$ = -8 ; size = 8 216 25.2. FLOAT POINT VALUES CHAPTER 25. TEMPERATURE CONVERTING _main PROC sub esp, 8 push esi mov esi, DWORD PTR __imp__printf push OFFSET $SG4228 ; ’Enter temperature in Fahrenheit:’ call esi ; call printf lea eax, DWORD PTR _fahr$[esp+16] push eax push OFFSET $SG4230 ; ’%lf’ call DWORD PTR __imp__scanf add esp, 12 ; 0000000cH cmp eax, 1 je SHORT $LN2@main push OFFSET $SG4231 ; ’Error while parsing your input’ call esi ; call printf add esp, 4 push 0 call DWORD PTR __imp__exit $LN9@main: $LN2@main: movsd xmm1, QWORD PTR _fahr$[esp+12] subsd xmm1, QWORD PTR __real@4040000000000000 ; 32 movsd xmm0, QWORD PTR __real@c071100000000000 ; -273 mulsd xmm1, QWORD PTR __real@4014000000000000 ; 5 divsd xmm1, QWORD PTR __real@4022000000000000 ; 9 comisd xmm0, xmm1 jbe SHORT $LN1@main push OFFSET $SG4233 ; ’Error: incorrect temperature!’ call esi ; call printf add esp, 4 push 0 call DWORD PTR __imp__exit $LN10@main: $LN1@main: sub esp, 8 movsd QWORD PTR [esp], xmm1 push OFFSET $SG4234 ; ’Celsius: %lf’ call esi ; call printf add esp, 12 ; 0000000cH ; return 0 xor eax, eax pop esi add esp, 8 ret 0 $LN8@main: _main ENDP Of course, SIMD instructions are available in x86 mode, including those working with floating point numbers. It’s some- what easier to use them for calculations, so the new Microso compiler use them. We may also notice that −273 value is loaded into XMM0 register too early. And that’s OK, because, compiler may emit instructions not in the order they are in source code. 217 CHAPTER 26. C99 RESTRICT Chapter 26 C99 restrict Here is a reason why FORTRAN programs, in some cases, works faster than C/C++ ones. void f1 (int* x, int* y, int* sum, int* product, int* sum_product, int* update_me, size_t s) { for (int i=0; i int celsius_to_fahrenheit (int celsius) { return celsius * 9 / 5 + 32; }; int main(int argc, char *argv[]) { int celsius=atol(argv[1]); printf ("%d\n", celsius_to_fahrenheit (celsius)); }; ... is compiled in very predictable way, however, if to turn on GCC optimization (-O3), we’ll see: Listing 27.2: GCC 4.8.1 -O3 _main: push ebp mov ebp, esp and esp, -16 sub esp, 16 call ___main mov eax, DWORD PTR [ebp+12] mov eax, DWORD PTR [eax+4] mov DWORD PTR [esp], eax call _atol mov edx, 1717986919 mov DWORD PTR [esp], OFFSET FLAT:LC2 ; "%d\12\0" lea ecx, [eax+eax*8] mov eax, ecx imul edx sar ecx, 31 sar edx sub edx, ecx add edx, 32 mov DWORD PTR [esp+4], edx call _printf leave ret (Here division is done by multiplication(14).) Yes, our small function was just placed before printf() call. Why? It may be faster than executing this function’s code plus calling/returning overhead. 221 CHAPTER 27. INLINE FUNCTIONS In past, such function must be marked with “inline” keyword in function’s declaration, however, in modern times, these functions are chosen automatically by compiler. Another very common automatic optimization is inlining of string functions like strcpy(), strcmp(), etc. Listing 27.3: Another simple example bool is_bool (char *s) { if (strcmp (s, "true")==0) return true; if (strcmp (s, "false")==0) return false; assert(0); }; Listing 27.4: GCC 4.8.1 -O3 _is_bool: push edi mov ecx, 5 push esi mov edi, OFFSET FLAT:LC0 ; "true\0" sub esp, 20 mov esi, DWORD PTR [esp+32] repz cmpsb je L3 mov esi, DWORD PTR [esp+32] mov ecx, 6 mov edi, OFFSET FLAT:LC1 ; "false\0" repz cmpsb seta cl setb dl xor eax, eax cmp cl, dl jne L8 add esp, 20 pop esi pop edi ret Here is an example of very frequently seen piece of strcmp() code generated by MSVC: Listing 27.5: MSVC mov dl, [eax] cmp dl, [ecx] jnz short loc_10027FA0 test dl, dl jz short loc_10027F9C mov dl, [eax+1] cmp dl, [ecx+1] jnz short loc_10027FA0 add eax, 2 add ecx, 2 test dl, dl jnz short loc_10027F80 loc_10027F9C: ; CODE XREF: f1+448 xor eax, eax jmp short loc_10027FA5 loc_10027FA0: ; CODE XREF: f1+444 ; f1+450 222 CHAPTER 27. INLINE FUNCTIONS sbb eax, eax sbb eax, 0FFFFFFFFh I wrote small IDA script for searching and folding such very frequently seen pieces of inline code: https://github.com/yurichev/IDA_scripts. 223 CHAPTER 28. INCORRECTLY DISASSEMBLED CODE Chapter 28 Incorrectly disassembled code Practicing reverse engineers o en dealing with incorrectly disassembled code. 28.1 Disassembling started incorrectly (x86) Unlike ARM and MIPS (where any instruction has length of 2 or 4 bytes), x86 instructions has variable size, so, any disassem- bler, starting at the middle of x86 instruction, may produce incorrect results. As an example: add [ebp-31F7Bh], cl dec dword ptr [ecx-3277Bh] dec dword ptr [ebp-2CF7Bh] inc dword ptr [ebx-7A76F33Ch] fdiv st(4), st db 0FFh dec dword ptr [ecx-21F7Bh] dec dword ptr [ecx-22373h] dec dword ptr [ecx-2276Bh] dec dword ptr [ecx-22B63h] dec dword ptr [ecx-22F4Bh] dec dword ptr [ecx-23343h] jmp dword ptr [esi-74h] xchg eax, ebp clc std db 0FFh db 0FFh mov word ptr [ebp-214h], cs mov word ptr [ebp-238h], ds mov word ptr [ebp-23Ch], es mov word ptr [ebp-240h], fs mov word ptr [ebp-244h], gs pushf pop dword ptr [ebp-210h] mov eax, [ebp+4] mov [ebp-218h], eax lea eax, [ebp+4] mov [ebp-20Ch], eax mov dword ptr [ebp-2D0h], 10001h mov eax, [eax-4] mov [ebp-21Ch], eax mov eax, [ebp+0Ch] mov [ebp-320h], eax mov eax, [ebp+10h] mov [ebp-31Ch], eax mov eax, [ebp+4] mov [ebp-314h], eax 224 28.2. HOW RANDOM NOISE LOOKS DISASSEMBLED? CHAPTER 28. INCORRECTLY DISASSEMBLED CODE call ds:IsDebuggerPresent mov edi, eax lea eax, [ebp-328h] push eax call sub_407663 pop ecx test eax, eax jnz short loc_402D7B There are incorrectly disassembled instructions at the beginning, but eventually, disassembler finds right track. 28.2 How random noise looks disassembled? Common properties which can be easily spotted are: • Unusually big instruction dispersion. Most frequent x86 instructions are PUSH, MOV, CALL, but here we will see in- structions from any instruction group: FPU instructions, IN/OUT instructions, rare and system instructions, everything messed up in one single place. • Big and random values, osets and immediates. • Jumps having incorrect osets o en jumping into the middle of another instructions. Listing 28.1: random noise (x86) mov bl, 0Ch mov ecx, 0D38558Dh mov eax, ds:2C869A86h db 67h mov dl, 0CCh insb movsb push eax xor [edx-53h], ah fcom qword ptr [edi-45A0EF72h] pop esp pop ss in eax, dx dec ebx push esp lds esp, [esi-41h] retf rcl dword ptr [eax], cl mov cl, 9Ch mov ch, 0DFh push cs insb mov esi, 0D9C65E4Dh imul ebp, [ecx], 66h pushf sal dword ptr [ebp-64h], cl sub eax, 0AC433D64h out 8Ch, eax pop ss sbb [eax], ebx aas xchg cl, [ebx+ebx*4+14B31Eh] jecxz short near ptr loc_58+1 xor al, 0C6h inc edx db 36h pusha 225 28.2. HOW RANDOM NOISE LOOKS DISASSEMBLED? CHAPTER 28. INCORRECTLY DISASSEMBLED CODE stosb test [ebx], ebx sub al, 0D3h ; ’L’ pop eax stosb loc_58: ; CODE XREF: seg000:0000004A test [esi], eax inc ebp das db 64h pop ecx das hlt pop edx out 0B0h, al lodsb push ebx cdq out dx, al sub al, 0Ah sti outsd add dword ptr [edx], 96FCBE4Bh and eax, 0E537EE4Fh inc esp stosd cdq push ecx in al, 0CBh mov ds:0D114C45Ch, al mov esi, 659D1985h enter 6FE8h, 0D9h enter 6FE6h, 0D9h xchg eax, esi sub eax, 0A599866Eh retn pop eax dec eax adc al, 21h ; ’!’ lahf inc edi sub eax, 9062EE5Bh bound eax, [ebx] loc_A2: ; CODE XREF: seg000:00000120 wait iret jnb short loc_D7 cmpsd iret jnb short loc_D7 sub ebx, [ecx] in al, 0Ch add esp, esp mov bl, 8Fh xchg eax, ecx 226 28.2. HOW RANDOM NOISE LOOKS DISASSEMBLED? CHAPTER 28. INCORRECTLY DISASSEMBLED CODE int 67h pop ds pop ebx db 36h xor esi, [ebp-4Ah] mov ebx, 0EB4F980Ch repne add bl, dh imul ebx, [ebp+5616E7A5h], 67A4D1EEh xchg eax, ebp scasb push esp wait mov dl, 11h mov ah, 29h ; ’)’ fist dword ptr [edx] loc_D7: ; CODE XREF: seg000:000000A4 ; seg000:000000A8 ... dec dword ptr [ebp-5D0E0BA4h] call near ptr 622FEE3Eh sbb ax, 5A2Fh jmp dword ptr cs:[ebx] xor ch, [edx-5] inc esp push edi xor esp, [ebx-6779D3B8h] pop eax int 3 ; Trap to Debugger rcl byte ptr [ebx-3Eh], cl xor [edi], bl sbb al, [edx+ecx*4] xor ah, [ecx-1DA4E05Dh] push edi xor ah, cl popa cmp dword ptr [edx-62h], 46h ; ’F’ dec eax in al, 69h dec ebx iret or al, 6 jns short near ptr loc_D7+3 shl byte ptr [esi], 42h repne adc [ebx+2Ch], eax icebp cmpsd leave push esi jmp short loc_A2 and eax, 0F2E41FE9h push esi loop loc_14F add ah, fs:[edx] loc_12D: ; CODE XREF: seg000:00000169 mov dh, 0F7h add [ebx+7B61D47Eh], esp mov edi, 79F19525h 227 28.2. HOW RANDOM NOISE LOOKS DISASSEMBLED? CHAPTER 28. INCORRECTLY DISASSEMBLED CODE rcl byte ptr [eax+22015F55h], cl cli sub al, 0D2h ; ’T’ dec eax mov ds:0A81406F5h, eax sbb eax, 0A7AA179Ah in eax, dx loc_14F: ; CODE XREF: seg000:00000128 and [ebx-4CDFAC74h], ah pop ecx push esi mov bl, 2Dh ; ’-’ in eax, 2Ch stosd inc edi push esp locret_15E: ; CODE XREF: seg000:loc_1A0 retn 0C432h and al, 86h cwde and al, 8Fh cmp ebp, [ebp+7] jz short loc_12D sub bh, ch or dword ptr [edi-7Bh], 8A16C0F7h db 65h insd mov al, ds:0A3A5173Dh dec ecx push ds xor al, cl jg short loc_195 push 6Eh ; ’n’ out 0DDh, al inc edi sub eax, 6899BBF1h leave rcr dword ptr [ecx-69h], cl sbb ch, [edi+5EDDCB54h] loc_195: ; CODE XREF: seg000:0000017F push es repne sub ah, [eax-105FF22Dh] cmc and ch, al loc_1A0: ; CODE XREF: seg000:00000217 jnp short near ptr locret_15E+1 or ch, [eax-66h] add [edi+edx-35h], esi out dx, al db 2Eh call far ptr 1AAh:6832F5DDh jz short near ptr loc_1DA+1 sbb esp, [edi+2CB02CEFh] xchg eax, edi xor [ebx-766342ABh], edx 228 28.2. HOW RANDOM NOISE LOOKS DISASSEMBLED? CHAPTER 28. INCORRECTLY DISASSEMBLED CODE loc_1C1: ; CODE XREF: seg000:00000212 cmp eax, 1BE9080h add [ecx], edi aad 0 imul esp, [edx-70h], 0A8990126h or dword ptr [edx+10C33693h], 4Bh popf loc_1DA: ; CODE XREF: seg000:000001B2 mov ecx, cs aaa mov al, 39h ; ’9’ adc byte ptr [eax-77F7F1C5h], 0C7h add [ecx], bl retn 0DD42h db 3Eh mov fs:[edi], edi and [ebx-24h], esp db 64h xchg eax, ebp push cs adc eax, [edi+36h] mov bh, 0C7h sub eax, 0A710CBE7h xchg eax, ecx or eax, 51836E42h xchg eax, ebx inc ecx jb short near ptr loc_21E+3 db 64h xchg eax, esp and dh, [eax-31h] mov ch, 13h add ebx, edx jnb short loc_1C1 db 65h adc al, 0C5h js short loc_1A0 sbb eax, 887F5BEEh loc_21E: ; CODE XREF: seg000:00000207 mov eax, 888E1FD6h mov bl, 90h cmp [eax], ecx rep int 61h ; reserved for user interrupt and edx, [esi-7EB5C9EAh] fisttp qword ptr [eax+esi*4+38F9BA6h] jmp short loc_27C fadd st, st(2) db 3Eh mov edx, 54C03172h retn db 64h pop ds xchg eax, esi rcr ebx, cl cmp [di+2Eh], ebx repne xor [di-19h], dh 229 28.2. HOW RANDOM NOISE LOOKS DISASSEMBLED? CHAPTER 28. INCORRECTLY DISASSEMBLED CODE insd adc dl, [eax-0C4579F7h] push ss xor [ecx+edx*4+65h], ecx mov cl, [ecx+ebx-32E8AC51h] or [ebx], ebp cmpsb lodsb iret Listing 28.2: random noise (x86-64) lea esi, [rax+rdx*4+43558D29h] loc_AF3: ; CODE XREF: seg000:0000000000000B46 rcl byte ptr [rsi+rax*8+29BB423Ah], 1 lea ecx, cs:0FFFFFFFFB2A6780Fh mov al, 96h mov ah, 0CEh push rsp lods byte ptr [esi] db 2Fh ; / pop rsp db 64h retf 0E993h cmp ah, [rax+4Ah] movzx rsi, dword ptr [rbp-25h] push 4Ah movzx rdi, dword ptr [rdi+rdx*8] db 9Ah rcr byte ptr [rax+1Dh], cl lodsd xor [rbp+6CF20173h], edx xor [rbp+66F8B593h], edx push rbx sbb ch, [rbx-0Fh] stosd int 87h db 46h, 4Ch out 33h, rax xchg eax, ebp test ecx, ebp movsd leave push rsp db 16h xchg eax, esi pop rdi loc_B3D: ; CODE XREF: seg000:0000000000000B5F mov ds:93CA685DF98A90F9h, eax jnz short near ptr loc_AF3+6 out dx, eax cwde 230 28.2. HOW RANDOM NOISE LOOKS DISASSEMBLED? CHAPTER 28. INCORRECTLY DISASSEMBLED CODE mov bh, 5Dh ; ’]’ movsb pop rbp db 60h ; ‘ movsxd rbp, dword ptr [rbp-17h] pop rbx out 7Dh, al add eax, 0D79BE769h db 1Fh retf 0CAB9h jl short near ptr loc_B3D+4 sal dword ptr [rbx+rbp+4Dh], 0D3h mov cl, 41h ; ’A’ imul eax, [rbp-5B77E717h], 1DDE6E5h imul ecx, ebx, 66359BCCh xlat db 60h ; ‘ cmp bl, [rax] and ebp, [rcx-57h] stc sub [rcx+1A533AB4h], al jmp short loc_C05 db 4Bh ; K int 3 ; Trap to Debugger xchg ebx, [rsp+rdx-5Bh] db 0D6h mov esp, 0C5BA61F7h out 0A3h, al ; Interrupt Controller #2, 8259A add al, 0A6h pop rbx cmp bh, fs:[rsi] and ch, cl cmp al, 0F3h db 0Eh xchg dh, [rbp+rax*4-4CE9621Ah] stosd xor [rdi], ebx stosb xchg eax, ecx push rsi insd fidiv word ptr [rcx] xchg eax, ecx mov dh, 0C0h ; ’L’ xchg eax, esp push rsi mov dh, [rdx+rbp+6918F1F3h] xchg eax, ebp 231 28.2. HOW RANDOM NOISE LOOKS DISASSEMBLED? CHAPTER 28. INCORRECTLY DISASSEMBLED CODE out 9Dh, al loc_BC0: ; CODE XREF: seg000:0000000000000C26 or [rcx-0Dh], ch int 67h ; - LIM EMS push rdx sub al, 43h ; ’C’ test ecx, ebp test [rdi+71F372A4h], cl db 7 imul ebx, [rsi-0Dh], 2BB30231h xor ebx, [rbp-718B6E64h] jns short near ptr loc_C56+1 ficomp dword ptr [rcx-1Ah] and eax, 69BEECC7h mov esi, 37DA40F6h imul r13, [rbp+rdi*8+529F33CDh], 0FFFFFFFFF35CDD30h or [rbx], edx imul esi, [rbx-34h], 0CDA42B87h db 36h ; 6 db 1Fh loc_C05: ; CODE XREF: seg000:0000000000000B86 add dh, [rcx] mov edi, 0DD3E659h ror byte ptr [rdx-33h], cl xlat db 48h sub rsi, [rcx] db 1Fh db 6 xor [rdi+13F5F362h], bh cmpsb sub esi, [rdx] pop rbp sbb al, 62h ; ’b’ mov dl, 33h ; ’3’ db 4Dh ; M db 17h jns short loc_BC0 push 0FFFFFFFFFFFFFF86h loc_C2A: ; CODE XREF: seg000:0000000000000C8F sub [rdi-2Ah], eax db 0FEh cmpsb wait rcr byte ptr [rax+5Fh], cl cmp bl, al pushfq xchg ch, cl 232 28.2. HOW RANDOM NOISE LOOKS DISASSEMBLED? CHAPTER 28. INCORRECTLY DISASSEMBLED CODE db 4Eh ; N db 37h ; 7 mov ds:0E43F3CCD3D9AB295h, eax cmp ebp, ecx jl short loc_C87 retn 8574h out 3, al ; DMA controller, 8237A-5. ; channel 1 base address and word count loc_C4C: ; CODE XREF: seg000:0000000000000C7F cmp al, 0A6h wait push 0FFFFFFFFFFFFFFBEh db 82h ficom dword ptr [rbx+r10*8] loc_C56: ; CODE XREF: seg000:0000000000000BDE jnz short loc_C76 xchg eax, edx db 26h wait iret push rcx db 48h ; H db 9Bh db 64h ; d db 3Eh ; > db 2Fh ; / mov al, ds:8A7490CA2E9AA728h stc db 60h ; ‘ test [rbx+rcx], ebp int 3 ; Trap to Debugger xlat loc_C72: ; CODE XREF: seg000:0000000000000CC6 mov bh, 98h db 2Eh ; . db 0DFh loc_C76: ; CODE XREF: seg000:loc_C56 jl short loc_C91 sub ecx, 13A7CCF2h movsb jns short near ptr loc_C4C+1 cmpsd sub ah, ah cdq 233 28.2. HOW RANDOM NOISE LOOKS DISASSEMBLED? CHAPTER 28. INCORRECTLY DISASSEMBLED CODE db 6Bh ; k db 5Ah ; Z loc_C87: ; CODE XREF: seg000:0000000000000C45 or ecx, [rbx+6Eh] rep in eax, 0Eh ; DMA controller, 8237A-5. ; Clear mask registers. ; Any OUT enables all 4 channels. cmpsb jnb short loc_C2A loc_C91: ; CODE XREF: seg000:loc_C76 scasd add dl, [rcx+5FEF30E6h] enter 0FFFFFFFFFFFFC733h, 7Ch insd mov ecx, gs in al, dx out 2Dh, al mov ds:6599E434E6D96814h, al cmpsb push 0FFFFFFFFFFFFFFD6h popfq xor ecx, ebp db 48h insb test al, cl xor [rbp-7Bh], cl and al, 9Bh db 9Ah push rsp xor al, 8Fh cmp eax, 924E81B9h clc mov bh, 0DEh jbe short near ptr loc_C72+1 db 1Eh retn 8FCAh db 0C4h ; - loc_CCD: ; CODE XREF: seg000:0000000000000D22 adc eax, 7CABFBF8h db 38h ; 8 mov ebp, 9C3E66FCh push rbp dec byte ptr [rcx] sahf fidivr word ptr [rdi+2Ch] db 1Fh db 3Eh 234 28.2. HOW RANDOM NOISE LOOKS DISASSEMBLED? CHAPTER 28. INCORRECTLY DISASSEMBLED CODE xchg eax, esi loc_CE2: ; CODE XREF: seg000:0000000000000D5E mov ebx, 0C7AFE30Bh clc in eax, dx sbb bh, bl xchg eax, ebp db 3Fh ; ? cmp edx, 3EC3E4D7h push 51h db 3Eh pushfq jl short loc_D17 test [rax-4CFF0D49h], ebx db 2Fh ; / rdtsc jns short near ptr loc_D40+4 mov ebp, 0B2BB03D8h in eax, dx db 1Eh fsubr dword ptr [rbx-0Bh] jns short loc_D70 scasd mov ch, 0C1h ; ’+’ add edi, [rbx-53h] db 0E7h loc_D17: ; CODE XREF: seg000:0000000000000CF7 jp short near ptr unk_D79 scasd cmc sbb ebx, [rsi] fsubr dword ptr [rbx+3Dh] retn db 3 jnp short near ptr loc_CCD+4 db 36h adc r14b, r13b db 1Fh retf test [rdi+rdi*2], ebx cdq or ebx, edi test eax, 310B94BCh ffreep st(7) cwde sbb esi, [rdx+53h] 235 28.2. HOW RANDOM NOISE LOOKS DISASSEMBLED? CHAPTER 28. INCORRECTLY DISASSEMBLED CODE push 5372CBAAh loc_D40: ; CODE XREF: seg000:0000000000000D02 push 53728BAAh push 0FFFFFFFFF85CF2FCh db 0Eh retn 9B9Bh movzx r9, dword ptr [rdx] adc [rcx+43h], ebp in al, 31h db 37h ; 7 jl short loc_DC5 icebp sub esi, [rdi] clc pop rdi jb short near ptr loc_CE2+1 or al, 8Fh mov ecx, 770EFF81h sub al, ch sub al, 73h ; ’s’ cmpsd adc bl, al out 87h, eax ; DMA page register 74LS612: ; Channel 0 (address bits 16-23) loc_D70: ; CODE XREF: seg000:0000000000000D0E adc edi, ebx db 49h outsb enter 33E5h, 97h xchg eax, ebx unk_D79 db 0FEh ; CODE XREF: seg000:loc_D17 db 0BEh db 0E1h db 82h loc_D7D: ; CODE XREF: seg000:0000000000000DB3 cwde db 7 db 5Ch ; \ db 10h db 73h ; s db 0A9h db 2Bh ; + db 9Fh loc_D85: ; CODE XREF: seg000:0000000000000DD1 dec dh jnz short near ptr loc_DD3+3 mov ds:7C1758CB282EF9BFh, al sal ch, 91h 236 28.2. HOW RANDOM NOISE LOOKS DISASSEMBLED? CHAPTER 28. INCORRECTLY DISASSEMBLED CODE rol dword ptr [rbx+7Fh], cl fbstp tbyte ptr [rcx+2] repne mov al, ds:4BFAB3C3ECF2BE13h pushfq imul edx, [rbx+rsi*8+3B484EE9h], 8EDC09C6h cmp [rax], al jg short loc_D7D xor [rcx-638C1102h], edx test eax, 14E3AD7h insd db 38h ; 8 db 80h db 0C3h loc_DC5: ; CODE XREF: seg000:0000000000000D57 ; seg000:0000000000000DD8 cmp ah, [rsi+rdi*2+527C01D3h] sbb eax, 5FC631F0h jnb short loc_D85 loc_DD3: ; CODE XREF: seg000:0000000000000D87 call near ptr 0FFFFFFFFC03919C7h loope near ptr loc_DC5+3 sbb al, 0C8h std Listing 28.3: random noise (ARM in ARM mode) BLNE 0xFE16A9D8 BGE 0x1634D0C SVCCS 0x450685 STRNVT R5, [PC],#-0x964 LDCGE p6, c14, [R0],#0x168 STCCSL p9, c9, [LR],#0x14C CMNHIP PC, R10,LSL#22 FLDMIADNV LR!, {D4} MCR p5, 2, R2,c15,c6, 4 BLGE 0x1139558 BLGT 0xFF9146E4 STRNEB R5, [R4],#0xCA2 STMNEIB R5, {R0,R4,R6,R7,R9-SP,PC} STMIA R8, {R0,R2-R4,R7,R8,R10,SP,LR}^ STRB SP, [R8],PC,ROR#18 LDCCS p9, c13, [R6,#0x1BC] LDRGE R8, [R9,#0x66E] STRNEB R5, [R8],#-0x8C3 STCCSL p15, c9, [R7,#-0x84] RSBLS LR, R2, R11,ASR LR SVCGT 0x9B0362 SVCGT 0xA73173 STMNEDB R11!, {R0,R1,R4-R6,R8,R10,R11,SP} STR R0, [R3],#-0xCE4 LDCGT p15, c8, [R1,#0x2CC] LDRCCB R1, [R11],-R7,ROR#30 BLLT 0xFED9D58C BL 0x13E60F4 LDMVSIB R3!, {R1,R4-R7}^ USATNE R10, #7, SP,LSL#11 LDRGEB LR, [R1],#0xE56 237 28.2. HOW RANDOM NOISE LOOKS DISASSEMBLED? CHAPTER 28. INCORRECTLY DISASSEMBLED CODE STRPLT R9, [LR],#0x567 LDRLT R11, [R1],#-0x29B SVCNV 0x12DB29 MVNNVS R5, SP,LSL#25 LDCL p8, c14, [R12,#-0x288] STCNEL p2, c6, [R6,#-0xBC]! SVCNV 0x2E5A2F BLX 0x1A8C97E TEQGE R3, #0x1100000 STMLSIA R6, {R3,R6,R10,R11,SP} BICPLS R12, R2, #0x5800 BNE 0x7CC408 TEQGE R2, R4,LSL#20 SUBS R1, R11, #0x28C BICVS R3, R12, R7,ASR R0 LDRMI R7, [LR],R3,LSL#21 BLMI 0x1A79234 STMVCDB R6, {R0-R3,R6,R7,R10,R11} EORMI R12, R6, #0xC5 MCRRCS p1, 0xF, R1,R3,c2 Listing 28.4: random noise (ARM in Thumb mode) LSRS R3, R6, #0x12 LDRH R1, [R7,#0x2C] SUBS R0, #0x55 ; ’U’ ADR R1, loc_3C LDR R2, [SP,#0x218] CMP R4, #0x86 SXTB R7, R4 LDR R4, [R1,#0x4C] STR R4, [R4,R2] STR R0, [R6,#0x20] BGT 0xFFFFFF72 LDRH R7, [R2,#0x34] LDRSH R0, [R2,R4] LDRB R2, [R7,R2] DCB 0x17 DCB 0xED STRB R3, [R1,R1] STR R5, [R0,#0x6C] LDMIA R3, {R0-R5,R7} ASRS R3, R2, #3 LDR R4, [SP,#0x2C4] SVC 0xB5 LDR R6, [R1,#0x40] LDR R5, =0xB2C5CA32 STMIA R6, {R1-R4,R6} LDR R1, [R3,#0x3C] STR R1, [R5,#0x60] BCC 0xFFFFFF70 LDR R4, [SP,#0x1D4] STR R5, [R5,#0x40] ORRS R5, R7 loc_3C ; DATA XREF: ROM:00000006 B 0xFFFFFF98 ASRS R4, R1, #0x1E 238 28.2. HOW RANDOM NOISE LOOKS DISASSEMBLED? CHAPTER 28. INCORRECTLY DISASSEMBLED CODE ADDS R1, R3, R0 STRH R7, [R7,#0x30] LDR R3, [SP,#0x230] CBZ R6, loc_90 MOVS R4, R2 LSRS R3, R4, #0x17 STMIA R6!, {R2,R4,R5} ADDS R6, #0x42 ; ’B’ ADD R2, SP, #0x180 SUBS R5, R0, R6 BCC loc_B0 ADD R2, SP, #0x160 LSLS R5, R0, #0x1A CMP R7, #0x45 LDR R4, [R4,R5] DCB 0x2F ; / DCB 0xF4 B 0xFFFFFD18 ADD R4, SP, #0x2C0 LDR R1, [SP,#0x14C] CMP R4, #0xEE DCB 0xA DCB 0xFB STRH R7, [R5,#0xA] LDR R3, loc_78 DCB 0xBE ; - DCB 0xFC MOVS R5, #0x96 DCB 0x4F ; O DCB 0xEE B 0xFFFFFAE6 ADD R3, SP, #0x110 loc_78 ; DATA XREF: ROM:0000006C STR R1, [R3,R6] LDMIA R3!, {R2,R5-R7} LDRB R2, [R4,R2] ASRS R4, R0, #0x13 BKPT 0xD1 ADDS R5, R0, R6 STR R5, [R3,#0x58] Listing 28.5: random noise(MIPS little endian) lw $t9, 0xCB3($t5) sb $t5, 0x3855($t0) sltiu $a2, $a0, -0x657A ldr $t4, -0x4D99($a2) daddi $s0, $s1, 0x50A4 lw $s7, -0x2353($s4) bgtzl $a1, 0x17C5C 239 28.2. HOW RANDOM NOISE LOOKS DISASSEMBLED? CHAPTER 28. INCORRECTLY DISASSEMBLED CODE .byte 0x17 .byte 0xED .byte 0x4B # K .byte 0x54 # T lwc2 $31, 0x66C5($sp) lwu $s1, 0x10D3($a1) ldr $t6, -0x204B($zero) lwc1 $f30, 0x4DBE($s2) daddiu $t1, $s1, 0x6BD9 lwu $s5, -0x2C64($v1) cop0 0x13D642D bne $gp, $t4, 0xFFFF9EF0 lh $ra, 0x1819($s1) sdl $fp, -0x6474($t8) jal 0x78C0050 ori $v0, $s2, 0xC634 blez $gp, 0xFFFEA9D4 swl $t8, -0x2CD4($s2) sltiu $a1, $k0, 0x685 sdc1 $f15, 0x5964($at) sw $s0, -0x19A6($a1) sltiu $t6, $a3, -0x66AD lb $t7, -0x4F6($t3) sd $fp, 0x4B02($a1) .byte 0x96 .byte 0x25 # % .byte 0x4F # O .byte 0xEE swl $a0, -0x1AC9($k0) lwc2 $4, 0x5199($ra) bne $a2, $a0, 0x17308 .byte 0xD1 .byte 0xBE .byte 0x85 .byte 0x19 swc2 $8, 0x659D($a2) swc1 $f8, -0x2691($s6) sltiu $s6, $t4, -0x2691 sh $t9, -0x7992($t4) bne $v0, $t0, 0x163A4 sltiu $a3, $t2, -0x60DF lbu $v0, -0x11A5($v1) pref 0x1B, 0x362($gp) pref 7, 0x3173($sp) blez $t1, 0xB678 swc1 $f3, flt_CE4($zero) pref 0x11, -0x704D($t4) ori $k1, $s2, 0x1F67 swr $s6, 0x7533($sp) swc2 $15, -0x67F4($k0) ldl $s3, 0xF2($t7) bne $s7, $a3, 0xFFFE973C sh $s1, -0x11AA($a2) bnel $a1, $t6, 0xFFFE566C sdr $s1, -0x4D65($zero) 240 28.3. INFORMATION ENTROPY OF AVERAGE CODE CHAPTER 28. INCORRECTLY DISASSEMBLED CODE sd $s2, -0x24D7($t8) scd $s4, 0x5C8D($t7) .byte 0xA2 .byte 0xE8 .byte 0x5C # \ .byte 0xED bgtz $t3, 0x189A0 sd $t6, 0x5A2F($t9) sdc2 $10, 0x3223($k1) sb $s3, 0x5744($t9) lwr $a2, 0x2C48($a0) beql $fp, $s2, 0xFFFF3258 It is also important to keep in mind that cleverly constructed unpacking and decrypting code (including self-modifying) may looks like noise as well, nevertheless, it executes correctly. 28.3 Information entropy of average code ent utility results1. (Entropy of ideally compressed (or encrypted) file is 8 bits per byte; of zero file of arbitrary size if 0 bits per byte.) Here we can see that a code for CPU with 4-byte instructions (ARM in ARM mode and MIPS) is least eective in this sense. 28.3.1 x86 .text section of ntoskrnl.exe file from Windows 2003: Entropy = 6.662739 bits per byte. Optimum compression would reduce the size of this 593920 byte file by 16 percent. ... .text section of ntoskrnl.exe from Windows 7 x64: Entropy = 6.549586 bits per byte. Optimum compression would reduce the size of this 1685504 byte file by 18 percent. ... 28.3.2 ARM (Thumb) AngryBirds Classic: Entropy = 7.058766 bits per byte. Optimum compression would reduce the size of this 3336888 byte file by 11 percent. ... 28.3.3 ARM (ARM mode) Linux Kernel 3.8.0: Entropy = 6.036160 bits per byte. Optimum compression would reduce the size 1http://www.fourmilab.ch/random/ 241 28.3. INFORMATION ENTROPY OF AVERAGE CODE CHAPTER 28. INCORRECTLY DISASSEMBLED CODE of this 6946037 byte file by 24 percent. ... 28.3.4 MIPS (little endian) .text section of user32.dll from Windows NT 4: Entropy = 6.098227 bits per byte. Optimum compression would reduce the size of this 433152 byte file by 23 percent. .... 242 CHAPTER 29. C++ Chapter 29 C++ 29.1 Classes 29.1.1 Simple example Internally, C++ classes representation is almost the same as structures representation. Let’s try an example with two variables, two constructors and one method: #include class c { private: int v1; int v2; public: c() // default ctor { v1=667; v2=999; }; c(int a, int b) // ctor { v1=a; v2=b; }; void dump() { printf ("%d; %d\n", v1, v2); }; }; int main() { class c c1; class c c2(5,6); c1.dump(); c2.dump(); return 0; }; 243 29.1. CLASSES CHAPTER 29. C++ MSVC—x86 Here is how main() function looks like translated into assembly language: Listing 29.1: MSVC _c2$ = -16 ; size = 8 _c1$ = -8 ; size = 8 _main PROC push ebp mov ebp, esp sub esp, 16 lea ecx, DWORD PTR _c1$[ebp] call ??0c@@QAE@XZ ; c::c push 6 push 5 lea ecx, DWORD PTR _c2$[ebp] call ??0c@@QAE@HH@Z ; c::c lea ecx, DWORD PTR _c1$[ebp] call ?dump@c@@QAEXXZ ; c::dump lea ecx, DWORD PTR _c2$[ebp] call ?dump@c@@QAEXXZ ; c::dump xor eax, eax mov esp, ebp pop ebp ret 0 _main ENDP So what’s going on. For each object (instance of class c) 8 bytes allocated, that is exactly size of 2 variables storage. For c1 a default argumentless constructor ??0c@@QAE@XZ is called. For c2 another constructor ??0c@@QAE@HH@Z is called and two numbers are passed as arguments. A pointer to object (this in C++ terminology) is passed in the ECX register. This is called thiscall (29.1.1) —a pointer to object passing method. MSVC doing it using the ECX register. Needless to say, it is not a standardized method, other compilers could do it dier- ently, e.g., via first function argument (like GCC). Why these functions has so odd names? That’s name mangling. C++ class may contain several methods sharing the same name but having dierent arguments —that is polymorphism. And of course, dierent classes may own methods sharing the same name. Name mangling enable us to encode class name + method name + all method argument types in one ASCII-string, which is to be used as internal function name. That’s all because neither linker, nor DLLOS loader (mangled names may be among DLL exports as well) knows nothing about C++ or OOP1. dump() function called two times a er. Now let’s see constructors’ code: Listing 29.2: MSVC _this$ = -4 ; size = 4 ??0c@@QAE@XZ PROC ; c::c, COMDAT ; _this$ = ecx push ebp mov ebp, esp push ecx mov DWORD PTR _this$[ebp], ecx mov eax, DWORD PTR _this$[ebp] mov DWORD PTR [eax], 667 mov ecx, DWORD PTR _this$[ebp] mov DWORD PTR [ecx+4], 999 mov eax, DWORD PTR _this$[ebp] mov esp, ebp pop ebp ret 0 ??0c@@QAE@XZ ENDP ; c::c 1Object-Oriented Programming 244 29.1. CLASSES CHAPTER 29. C++ _this$ = -4 ; size = 4 _a$ = 8 ; size = 4 _b$ = 12 ; size = 4 ??0c@@QAE@HH@Z PROC ; c::c, COMDAT ; _this$ = ecx push ebp mov ebp, esp push ecx mov DWORD PTR _this$[ebp], ecx mov eax, DWORD PTR _this$[ebp] mov ecx, DWORD PTR _a$[ebp] mov DWORD PTR [eax], ecx mov edx, DWORD PTR _this$[ebp] mov eax, DWORD PTR _b$[ebp] mov DWORD PTR [edx+4], eax mov eax, DWORD PTR _this$[ebp] mov esp, ebp pop ebp ret 8 ??0c@@QAE@HH@Z ENDP ; c::c Constructors are just functions, they use pointer to structure in the ECX, moving the pointer into own local variable, how- ever, it is not necessary. From the C++ standard [16, 12.1] we know that constructors should not return any values. In fact, internally, constructors are returns pointer to the newly created object, i.e., this. Now dump() method: Listing 29.3: MSVC _this$ = -4 ; size = 4 ?dump@c@@QAEXXZ PROC ; c::dump, COMDAT ; _this$ = ecx push ebp mov ebp, esp push ecx mov DWORD PTR _this$[ebp], ecx mov eax, DWORD PTR _this$[ebp] mov ecx, DWORD PTR [eax+4] push ecx mov edx, DWORD PTR _this$[ebp] mov eax, DWORD PTR [edx] push eax push OFFSET ??_C@_07NJBDCIEC@?$CFd?$DL?5?$CFd?6?$AA@ call _printf add esp, 12 mov esp, ebp pop ebp ret 0 ?dump@c@@QAEXXZ ENDP ; c::dump Simple enough: dump()taking pointer to the structure containing twoint’s in theECX, takes two values from it and passing it into printf(). The code is much shorter if compiled with optimization (/Ox): Listing 29.4: MSVC ??0c@@QAE@XZ PROC ; c::c, COMDAT ; _this$ = ecx mov eax, ecx mov DWORD PTR [eax], 667 mov DWORD PTR [eax+4], 999 ret 0 ??0c@@QAE@XZ ENDP ; c::c 245 29.1. CLASSES CHAPTER 29. C++ _a$ = 8 ; size = 4 _b$ = 12 ; size = 4 ??0c@@QAE@HH@Z PROC ; c::c, COMDAT ; _this$ = ecx mov edx, DWORD PTR _b$[esp-4] mov eax, ecx mov ecx, DWORD PTR _a$[esp-4] mov DWORD PTR [eax], ecx mov DWORD PTR [eax+4], edx ret 8 ??0c@@QAE@HH@Z ENDP ; c::c ?dump@c@@QAEXXZ PROC ; c::dump, COMDAT ; _this$ = ecx mov eax, DWORD PTR [ecx+4] mov ecx, DWORD PTR [ecx] push eax push ecx push OFFSET ??_C@_07NJBDCIEC@?$CFd?$DL?5?$CFd?6?$AA@ call _printf add esp, 12 ret 0 ?dump@c@@QAEXXZ ENDP ; c::dump That’s all. One more thing to say is the stack pointer was not corrected with add esp, X a er constructor called. Withal, constructor has ret 8 instead of the RET at the end. This is all because here used thiscall (29.1.1) calling convention, the method of passing values through the stack, which is, together with stdcall (44.2) method, oers to correct stack to callee rather then to caller. ret x instruction adding X to the value in the ESP, then passes control to the caller function. See also section about calling conventions (44). It is also should be noted the compiler deciding when to call constructor and destructor —but that is we already know from C++ language basics. MSVC—x86-64 As we already know, first 4 function arguments in x86-64 are passed in RCX, RDX, R8, R9 registers, all the rest—via stack. Nevertheless, this pointer to the object is passed in RCX, first method argument—in EDX, etc. We can see this in the c(int a, int b) method internals: Listing 29.5: MSVC 2012 x64 /Ox ; void dump() ?dump@c@@QEAAXXZ PROC ; c::dump mov r8d, DWORD PTR [rcx+4] mov edx, DWORD PTR [rcx] lea rcx, OFFSET FLAT:??_C@_07NJBDCIEC@?$CFd?$DL?5?$CFd?6?$AA@ ; ’%d; %d’ jmp printf ?dump@c@@QEAAXXZ ENDP ; c::dump ; c(int a, int b) ??0c@@QEAA@HH@Z PROC ; c::c mov DWORD PTR [rcx], edx ; 1st argument: a mov DWORD PTR [rcx+4], r8d ; 2nd argument: b mov rax, rcx ret 0 ??0c@@QEAA@HH@Z ENDP ; c::c ; default ctor 246 29.1. CLASSES CHAPTER 29. C++ ??0c@@QEAA@XZ PROC ; c::c mov DWORD PTR [rcx], 667 mov DWORD PTR [rcx+4], 999 mov rax, rcx ret 0 ??0c@@QEAA@XZ ENDP ; c::c int data type is still 32-bit in x64 2, so that is why 32-bit register’s parts are used here. We also see JMP printf instead of RET in the dump() method, that hack we already saw earlier: 11.1.1. GCC—x86 It is almost the same situation in GCC 4.4.1, with a few exceptions. Listing 29.6: GCC 4.4.1 public main main proc near var_20 = dword ptr -20h var_1C = dword ptr -1Ch var_18 = dword ptr -18h var_10 = dword ptr -10h var_8 = dword ptr -8 push ebp mov ebp, esp and esp, 0FFFFFFF0h sub esp, 20h lea eax, [esp+20h+var_8] mov [esp+20h+var_20], eax call _ZN1cC1Ev mov [esp+20h+var_18], 6 mov [esp+20h+var_1C], 5 lea eax, [esp+20h+var_10] mov [esp+20h+var_20], eax call _ZN1cC1Eii lea eax, [esp+20h+var_8] mov [esp+20h+var_20], eax call _ZN1c4dumpEv lea eax, [esp+20h+var_10] mov [esp+20h+var_20], eax call _ZN1c4dumpEv mov eax, 0 leave retn main endp Here we see another name mangling style, specific to GNU 3 It is also can be noted the pointer to object is passed as first function argument —transparently from programmer, of course. First constructor: public _ZN1cC1Ev ; weak _ZN1cC1Ev proc near ; CODE XREF: main+10 arg_0 = dword ptr 8 push ebp mov ebp, esp mov eax, [ebp+arg_0] mov dword ptr [eax], 667 2Apparently, for easier porting of C/C++ 32-bit code to x64 3One more document about dierent compilers name mangling types: [12] standards. 247 29.1. CLASSES CHAPTER 29. C++ mov eax, [ebp+arg_0] mov dword ptr [eax+4], 999 pop ebp retn _ZN1cC1Ev endp What it does is just writes two numbers using pointer passed in first (and single) argument. Second constructor: public _ZN1cC1Eii _ZN1cC1Eii proc near arg_0 = dword ptr 8 arg_4 = dword ptr 0Ch arg_8 = dword ptr 10h push ebp mov ebp, esp mov eax, [ebp+arg_0] mov edx, [ebp+arg_4] mov [eax], edx mov eax, [ebp+arg_0] mov edx, [ebp+arg_8] mov [eax+4], edx pop ebp retn _ZN1cC1Eii endp This is a function, analog of which could be looks like: void ZN1cC1Eii (int *obj, int a, int b) { *obj=a; *(obj+1)=b; }; ...and that is completely predictable. Now dump() function: public _ZN1c4dumpEv _ZN1c4dumpEv proc near var_18 = dword ptr -18h var_14 = dword ptr -14h var_10 = dword ptr -10h arg_0 = dword ptr 8 push ebp mov ebp, esp sub esp, 18h mov eax, [ebp+arg_0] mov edx, [eax+4] mov eax, [ebp+arg_0] mov eax, [eax] mov [esp+18h+var_10], edx mov [esp+18h+var_14], eax mov [esp+18h+var_18], offset aDD ; "%d; %d\n" call _printf leave retn _ZN1c4dumpEv endp This function in its internal representation has sole argument, used as pointer to the object (this). 248 29.1. CLASSES CHAPTER 29. C++ Thus, if to base our judgment on these simple examples, the dierence between MSVC and GCC is style of function names encoding (name mangling) and passing pointer to object (via the ECX register or via the first argument). GCC—x86-64 The first 6 arguments, as we already know, are passed in the RDI, RSI, RDX, RCX, R8, R9 [21] registers, and the pointer to this via first one (RDI) and that is what we see here. int data type is also 32-bit here. JMP instead of RET hack is also used here. Listing 29.7: GCC 4.4.6 x64 ; default ctor _ZN1cC2Ev: mov DWORD PTR [rdi], 667 mov DWORD PTR [rdi+4], 999 ret ; c(int a, int b) _ZN1cC2Eii: mov DWORD PTR [rdi], esi mov DWORD PTR [rdi+4], edx ret ; dump() _ZN1c4dumpEv: mov edx, DWORD PTR [rdi+4] mov esi, DWORD PTR [rdi] xor eax, eax mov edi, OFFSET FLAT:.LC0 ; "%d; %d\n" jmp printf 29.1.2 Class inheritance It can be said about inherited classes that it is simple structure we already considered, but extending in inherited classes. Let’s take simple example: #include class object { public: int color; object() { }; object (int color) { this->color=color; }; void print_color() { printf ("color=%d\n", color); }; }; class box : public object { private: int width, height, depth; public: box(int color, int width, int height, int depth) { this->color=color; this->width=width; this->height=height; this->depth=depth; }; void dump() 249 29.1. CLASSES CHAPTER 29. C++ { printf ("this is box. color=%d, width=%d, height=%d, depth=%d\n", color, width, ⤦ Ç height, depth); }; }; class sphere : public object { private: int radius; public: sphere(int color, int radius) { this->color=color; this->radius=radius; }; void dump() { printf ("this is sphere. color=%d, radius=%d\n", color, radius); }; }; int main() { box b(1, 10, 20, 30); sphere s(2, 40); b.print_color(); s.print_color(); b.dump(); s.dump(); return 0; }; Let’s investigate generated code of the dump() functions/methods and also object::print_color(), let’s see memory layout for structures-objects (as of 32-bit code). So, dump() methods for several classes, generated by MSVC 2008 with /Ox and /Ob0 options 4 Listing 29.8: Optimizing MSVC 2008 /Ob0 ??_C@_09GCEDOLPA@color?$DN?$CFd?6?$AA@ DB ’color=%d’, 0aH, 00H ; ‘string’ ?print_color@object@@QAEXXZ PROC ; object::print_color, COMDAT ; _this$ = ecx mov eax, DWORD PTR [ecx] push eax ; ’color=%d’, 0aH, 00H push OFFSET ??_C@_09GCEDOLPA@color?$DN?$CFd?6?$AA@ call _printf add esp, 8 ret 0 ?print_color@object@@QAEXXZ ENDP ; object::print_color Listing 29.9: Optimizing MSVC 2008 /Ob0 ?dump@box@@QAEXXZ PROC ; box::dump, COMDAT ; _this$ = ecx mov eax, DWORD PTR [ecx+12] mov edx, DWORD PTR [ecx+8] 4/Ob0 options means inline expansion disabling since function inlining right into the code where the function is called will make our experiment harder 250 29.1. CLASSES CHAPTER 29. C++ push eax mov eax, DWORD PTR [ecx+4] mov ecx, DWORD PTR [ecx] push edx push eax push ecx ; ’this is box. color=%d, width=%d, height=%d, depth=%d’, 0aH, 00H ; ‘string’ push OFFSET ??_C@_0DG@NCNGAADL@this?5is?5box?4?5color?$DN?$CFd?0?5width?$DN?$CFd?0@ call _printf add esp, 20 ret 0 ?dump@box@@QAEXXZ ENDP ; box::dump Listing 29.10: Optimizing MSVC 2008 /Ob0 ?dump@sphere@@QAEXXZ PROC ; sphere::dump, COMDAT ; _this$ = ecx mov eax, DWORD PTR [ecx+4] mov ecx, DWORD PTR [ecx] push eax push ecx ; ’this is sphere. color=%d, radius=%d’, 0aH, 00H push OFFSET ??_C@_0CF@EFEDJLDC@this?5is?5sphere?4?5color?$DN?$CFd?0?5radius@ call _printf add esp, 12 ret 0 ?dump@sphere@@QAEXXZ ENDP ; sphere::dump So, here is memory layout: (base class object) oset description +0x0 int color (inherited classes) box: oset description +0x0 int color +0x4 int width +0x8 int height +0xC int depth sphere: oset description +0x0 int color +0x4 int radius Let’s see main() function body: Listing 29.11: Optimizing MSVC 2008 /Ob0 PUBLIC _main _TEXT SEGMENT _s$ = -24 ; size = 8 _b$ = -16 ; size = 16 _main PROC sub esp, 24 push 30 push 20 push 10 251 29.1. CLASSES CHAPTER 29. C++ push 1 lea ecx, DWORD PTR _b$[esp+40] call ??0box@@QAE@HHHH@Z ; box::box push 40 push 2 lea ecx, DWORD PTR _s$[esp+32] call ??0sphere@@QAE@HH@Z ; sphere::sphere lea ecx, DWORD PTR _b$[esp+24] call ?print_color@object@@QAEXXZ ; object::print_color lea ecx, DWORD PTR _s$[esp+24] call ?print_color@object@@QAEXXZ ; object::print_color lea ecx, DWORD PTR _b$[esp+24] call ?dump@box@@QAEXXZ ; box::dump lea ecx, DWORD PTR _s$[esp+24] call ?dump@sphere@@QAEXXZ ; sphere::dump xor eax, eax add esp, 24 ret 0 _main ENDP Inherited classes must always add their fields a er base classes’ fields, so to make possible for base class methods to work with their fields. When object::print_color() method is called, a pointers to both box object and sphere object are passed as this, it can work with these objects easily since color field in these objects is always at the pinned address (at +0x0 oset). It can be said, object::print_color() method is agnostic in relation to input object type as long as fields will be pinned at the same addresses, and this condition is always true. And if you create inherited class of the e.g. box class, compiler will add new fields a er depth field, leaving box class fields at the pinned addresses. Thus, box::dump()method will work fine accessingcolor/width/height/depthsfields always pinned on known addresses. GCC-generated code is almost likewise, with the sole exception of this pointer passing (as it was described above, it passing as first argument instead of the ECX registers. 29.1.3 Encapsulation Encapsulation is data hiding in the private sections of class, e.g. to allow access to them only from this class methods, but no more than. However, are there any marks in code about the fact that some field is private and some other —not? No, there are no such marks. Let’s try simple example: #include class box { private: int color, width, height, depth; public: box(int color, int width, int height, int depth) { this->color=color; this->width=width; this->height=height; this->depth=depth; }; void dump() { printf ("this is box. color=%d, width=%d, height=%d, depth=%d\n", color, width, ⤦ Ç height, depth); }; }; Let’s compile it again in MSVC 2008 with /Ox and /Ob0 options and let’s see box::dump() method code: 252 29.1. CLASSES CHAPTER 29. C++ ?dump@box@@QAEXXZ PROC ; box::dump, COMDAT ; _this$ = ecx mov eax, DWORD PTR [ecx+12] mov edx, DWORD PTR [ecx+8] push eax mov eax, DWORD PTR [ecx+4] mov ecx, DWORD PTR [ecx] push edx push eax push ecx ; ’this is box. color=%d, width=%d, height=%d, depth=%d’, 0aH, 00H push OFFSET ??_C@_0DG@NCNGAADL@this?5is?5box?4?5color?$DN?$CFd?0?5width?$DN?$CFd?0@ call _printf add esp, 20 ret 0 ?dump@box@@QAEXXZ ENDP ; box::dump Here is a memory layout of the class: oset description +0x0 int color +0x4 int width +0x8 int height +0xC int depth All fields are private and not allowed to access from any other functions, but, knowing this layout, can we create a code modifying these fields? So I added hack_oop_encapsulation() function, which, if has the body as follows, will not compile: void hack_oop_encapsulation(class box * o) { o->width=1; // that code can’t be compiled: // "error C2248: ’box::width’ : cannot access private member declared in class ⤦ Ç’box’" }; Nevertheless, if to cast box type to pointer to int array, and if to modify array of the int-s we got, then we have success. void hack_oop_encapsulation(class box * o) { unsigned int *ptr_to_object=reinterpret_cast(o); ptr_to_object[1]=123; }; This functions’ code is very simple —it can be said, the function taking pointer to array of the int-s on input and writing 123 to the second int: ?hack_oop_encapsulation@@YAXPAVbox@@@Z PROC ; hack_oop_encapsulation mov eax, DWORD PTR _o$[esp-4] mov DWORD PTR [eax+4], 123 ret 0 ?hack_oop_encapsulation@@YAXPAVbox@@@Z ENDP ; hack_oop_encapsulation Let’s check, how it works: int main() { box b(1, 10, 20, 30); b.dump(); hack_oop_encapsulation(&b); 253 29.1. CLASSES CHAPTER 29. C++ b.dump(); return 0; }; Let’s run: this is box. color=1, width=10, height=20, depth=30 this is box. color=1, width=123, height=20, depth=30 We see, encapsulation is just class fields protection only on compiling stage. C++ compiler will not allow to generate a code modifying protected fields straightforwardly, nevertheless, it is possible with the help of dirty hacks. 29.1.4 Multiple inheritance Multiple inheritance is a class creation which inherits fields and methods from two or more classes. Let’s write simple example again: #include class box { public: int width, height, depth; box() { }; box(int width, int height, int depth) { this->width=width; this->height=height; this->depth=depth; }; void dump() { printf ("this is box. width=%d, height=%d, depth=%d\n", width, height, depth); }; int get_volume() { return width * height * depth; }; }; class solid_object { public: int density; solid_object() { }; solid_object(int density) { this->density=density; }; int get_density() { return density; }; void dump() { printf ("this is solid_object. density=%d\n", density); }; }; class solid_box: box, solid_object { 254 29.1. CLASSES CHAPTER 29. C++ public: solid_box (int width, int height, int depth, int density) { this->width=width; this->height=height; this->depth=depth; this->density=density; }; void dump() { printf ("this is solid_box. width=%d, height=%d, depth=%d, density=%d\n", width, ⤦ Ç height, depth, density); }; int get_weight() { return get_volume() * get_density(); }; }; int main() { box b(10, 20, 30); solid_object so(100); solid_box sb(10, 20, 30, 3); b.dump(); so.dump(); sb.dump(); printf ("%d\n", sb.get_weight()); return 0; }; Let’s compile it in MSVC 2008 with/Oxand/Ob0options and let’s seebox::dump(),solid_object::dump()andsolid_box::dump() methods code: Listing 29.12: Optimizing MSVC 2008 /Ob0 ?dump@box@@QAEXXZ PROC ; box::dump, COMDAT ; _this$ = ecx mov eax, DWORD PTR [ecx+8] mov edx, DWORD PTR [ecx+4] push eax mov eax, DWORD PTR [ecx] push edx push eax ; ’this is box. width=%d, height=%d, depth=%d’, 0aH, 00H push OFFSET ??_C@_0CM@DIKPHDFI@this?5is?5box?4?5width?$DN?$CFd?0?5height?$DN?$CFd@ call _printf add esp, 16 ret 0 ?dump@box@@QAEXXZ ENDP ; box::dump Listing 29.13: Optimizing MSVC 2008 /Ob0 ?dump@solid_object@@QAEXXZ PROC ; solid_object::dump, COMDAT ; _this$ = ecx mov eax, DWORD PTR [ecx] push eax ; ’this is solid_object. density=%d’, 0aH push OFFSET ??_C@_0CC@KICFJINL@this?5is?5solid_object?4?5density?$DN?$CFd@ call _printf add esp, 8 ret 0 ?dump@solid_object@@QAEXXZ ENDP ; solid_object::dump 255 29.1. CLASSES CHAPTER 29. C++ Listing 29.14: Optimizing MSVC 2008 /Ob0 ?dump@solid_box@@QAEXXZ PROC ; solid_box::dump, COMDAT ; _this$ = ecx mov eax, DWORD PTR [ecx+12] mov edx, DWORD PTR [ecx+8] push eax mov eax, DWORD PTR [ecx+4] mov ecx, DWORD PTR [ecx] push edx push eax push ecx ; ’this is solid_box. width=%d, height=%d, depth=%d, density=%d’, 0aH push OFFSET ??_C@_0DO@HNCNIHNN@this?5is?5solid_box?4?5width?$DN?$CFd?0?5hei@ call _printf add esp, 20 ret 0 ?dump@solid_box@@QAEXXZ ENDP ; solid_box::dump So, the memory layout for all three classes is: box class: oset description +0x0 width +0x4 height +0x8 depth solid_object class: oset description +0x0 density It can be said, solid_box class memory layout will be united: solid_box class: oset description +0x0 width +0x4 height +0x8 depth +0xC density The code of the box::get_volume() and solid_object::get_density() methods is trivial: Listing 29.15: Optimizing MSVC 2008 /Ob0 ?get_volume@box@@QAEHXZ PROC ; box::get_volume, COMDAT ; _this$ = ecx mov eax, DWORD PTR [ecx+8] imul eax, DWORD PTR [ecx+4] imul eax, DWORD PTR [ecx] ret 0 ?get_volume@box@@QAEHXZ ENDP ; box::get_volume Listing 29.16: Optimizing MSVC 2008 /Ob0 ?get_density@solid_object@@QAEHXZ PROC ; solid_object::get_density, COMDAT ; _this$ = ecx mov eax, DWORD PTR [ecx] ret 0 ?get_density@solid_object@@QAEHXZ ENDP ; solid_object::get_density But the code of the solid_box::get_weight() method is much more interesting: 256 29.1. CLASSES CHAPTER 29. C++ Listing 29.17: Optimizing MSVC 2008 /Ob0 ?get_weight@solid_box@@QAEHXZ PROC ; solid_box::get_weight, COMDAT ; _this$ = ecx push esi mov esi, ecx push edi lea ecx, DWORD PTR [esi+12] call ?get_density@solid_object@@QAEHXZ ; solid_object::get_density mov ecx, esi mov edi, eax call ?get_volume@box@@QAEHXZ ; box::get_volume imul eax, edi pop edi pop esi ret 0 ?get_weight@solid_box@@QAEHXZ ENDP ; solid_box::get_weight get_weight() just calling two methods, but for get_volume() it just passing pointer to this, and for get_density() it passing pointer tothisshi ed by12(or0xC) bytes, and there, in thesolid_boxclass memory layout, fields of thesolid_object class are beginning. Thus,solid_object::get_density()method will believe it is dealing with usualsolid_objectclass, andbox::get_volume() method will work with its three fields, believing this is usual object of the box class. Thus, we can say, an object of a class, inheriting from several other classes, representing in memory united class, con- taining all inherited fields. And each inherited method called with a pointer to corresponding structure’s part passed. 29.1.5 Virtual methods Yet another simple example: #include class object { public: int color; object() { }; object (int color) { this->color=color; }; virtual void dump() { printf ("color=%d\n", color); }; }; class box : public object { private: int width, height, depth; public: box(int color, int width, int height, int depth) { this->color=color; this->width=width; this->height=height; this->depth=depth; }; void dump() { printf ("this is box. color=%d, width=%d, height=%d, depth=%d\n", color, width, ⤦ Ç height, depth); }; }; 257 29.1. CLASSES CHAPTER 29. C++ class sphere : public object { private: int radius; public: sphere(int color, int radius) { this->color=color; this->radius=radius; }; void dump() { printf ("this is sphere. color=%d, radius=%d\n", color, radius); }; }; int main() { box b(1, 10, 20, 30); sphere s(2, 40); object *o1=&b; object *o2=&s; o1->dump(); o2->dump(); return 0; }; Class object has virtual method dump(), being replaced in the box and sphere class-inheritors. If in an environment, where it is not known what type has object, as in the main() function in example, a virtual method dump() is called, somewhere, the information about its type must be stored, so to call relevant virtual method. Let’s compile it in MSVC 2008 with /Ox and /Ob0 options and let’s see main() function code: _s$ = -32 ; size = 12 _b$ = -20 ; size = 20 _main PROC sub esp, 32 push 30 push 20 push 10 push 1 lea ecx, DWORD PTR _b$[esp+48] call ??0box@@QAE@HHHH@Z ; box::box push 40 push 2 lea ecx, DWORD PTR _s$[esp+40] call ??0sphere@@QAE@HH@Z ; sphere::sphere mov eax, DWORD PTR _b$[esp+32] mov edx, DWORD PTR [eax] lea ecx, DWORD PTR _b$[esp+32] call edx mov eax, DWORD PTR _s$[esp+32] mov edx, DWORD PTR [eax] lea ecx, DWORD PTR _s$[esp+32] call edx xor eax, eax add esp, 32 ret 0 _main ENDP 258 29.1. CLASSES CHAPTER 29. C++ Pointer to the dump() function is taken somewhere from object. Where the address of new method would be written there? Only somewhere in constructors: there is no other place since nothing more is called in the main() function. 5 Let’s see box class constructor’s code: ??_R0?AVbox@@@8 DD FLAT:??_7type_info@@6B@ ; box ‘RTTI Type Descriptor’ DD 00H DB ’.?AVbox@@’, 00H ??_R1A@?0A@EA@box@@8 DD FLAT:??_R0?AVbox@@@8 ; box::‘RTTI Base Class Descriptor at (0,-1,0,64)’ DD 01H DD 00H DD 0ffffffffH DD 00H DD 040H DD FLAT:??_R3box@@8 ??_R2box@@8 DD FLAT:??_R1A@?0A@EA@box@@8 ; box::‘RTTI Base Class Array’ DD FLAT:??_R1A@?0A@EA@object@@8 ??_R3box@@8 DD 00H ; box::‘RTTI Class Hierarchy Descriptor’ DD 00H DD 02H DD FLAT:??_R2box@@8 ??_R4box@@6B@ DD 00H ; box::‘RTTI Complete Object Locator’ DD 00H DD 00H DD FLAT:??_R0?AVbox@@@8 DD FLAT:??_R3box@@8 ??_7box@@6B@ DD FLAT:??_R4box@@6B@ ; box::‘vftable’ DD FLAT:?dump@box@@UAEXXZ _color$ = 8 ; size = 4 _width$ = 12 ; size = 4 _height$ = 16 ; size = 4 _depth$ = 20 ; size = 4 ??0box@@QAE@HHHH@Z PROC ; box::box, COMDAT ; _this$ = ecx push esi mov esi, ecx call ??0object@@QAE@XZ ; object::object mov eax, DWORD PTR _color$[esp] mov ecx, DWORD PTR _width$[esp] mov edx, DWORD PTR _height$[esp] mov DWORD PTR [esi+4], eax mov eax, DWORD PTR _depth$[esp] mov DWORD PTR [esi+16], eax mov DWORD PTR [esi], OFFSET ??_7box@@6B@ mov DWORD PTR [esi+8], ecx mov DWORD PTR [esi+12], edx mov eax, esi pop esi ret 16 ??0box@@QAE@HHHH@Z ENDP ; box::box Here we see slightly dierent memory layout: the first field is a pointer to some table box::‘vftable’ (name was set by MSVC compiler). In this table we see a link to the table namedbox::‘RTTI Complete Object Locator’and also a link to thebox::dump() method. So this is named virtual methods table and RTTI6. Table of virtual methods contain addresses of methods and RTTI 5About pointers to functions, read more in relevant section:(20) 6Run-time type information 259 29.2. OSTREAM CHAPTER 29. C++ table contain information about types. By the way, RTTI-tables are the tables enumerated while calling to dynamic_cast and typeid in C++. You can also see here class name as plain text string. Thus, a method of base object class may call vir- tual method object::dump(), which in turn, will call a method of inherited class since that information is present right in the object’s structure. Some additional CPU time needed for enumerating these tables and finding right virtual method address, thus virtual methods are widely considered as slightly slower than common methods. In GCC-generated code RTTI-tables constructed slightly dierently. 29.2 ostream Let’s start again with a “hello world” example, but now will use ostream: #include int main() { std::cout << "Hello, world!\n"; } Almost any C++ textbook tells that « operation can be replaced (overloaded) for other types. That is what is done in ostream. We see that operator« is called for ostream: Listing 29.18: MSVC 2012 (reduced listing) $SG37112 DB ’Hello, world!’, 0aH, 00H _main PROC push OFFSET $SG37112 push OFFSET ?cout@std@@3V?$basic_ostream@DU?$char_traits@D@std@@@1@A ; std::cout call ??$?6U?$char_traits@D@std@@@std@@YAAAV?$basic_ostream@DU?⤦ Ç $char_traits@D@std@@@0@AAV10@PBD@Z ; std::operator<< > add esp, 8 xor eax, eax ret 0 _main ENDP Let’s modify the example: #include int main() { std::cout << "Hello, " << "world!\n"; } And again, from many C++ textbooks we know that the result of each operator« in ostream is forwarded to the next one. Indeed: Listing 29.19: MSVC 2012 $SG37112 DB ’world!’, 0aH, 00H $SG37113 DB ’Hello, ’, 00H _main PROC push OFFSET $SG37113 ; ’Hello, ’ push OFFSET ?cout@std@@3V?$basic_ostream@DU?$char_traits@D@std@@@1@A ; std::cout call ??$?6U?$char_traits@D@std@@@std@@YAAAV?$basic_ostream@DU?⤦ Ç $char_traits@D@std@@@0@AAV10@PBD@Z ; std::operator<< > add esp, 8 push OFFSET $SG37112 ; ’world!’ push eax ; result of previous function execution call ??$?6U?$char_traits@D@std@@@std@@YAAAV?$basic_ostream@DU?⤦ Ç $char_traits@D@std@@@0@AAV10@PBD@Z ; std::operator<< > 260 29.3. REFERENCES CHAPTER 29. C++ add esp, 8 xor eax, eax ret 0 _main ENDP If to replace operator« by f(), that code can be rewritten as: f(f(std::cout, "Hello, "), "world!") GCC generates almost the same code as MSVC. 29.3 References In C++, references are pointers (9) as well, but they are called safe, because it is harder to make a mistake while dealing with them [16, 8.3.2]. For example, reference must always be pointing to the object of corresponding type and cannot be NULL [6, 8.6]. Even more than that, reference cannot be changed, it is impossible to point it to another object (reseat) [6, 8.5]. If we will try to change the pointers example (9) to use references instead of pointers: void f2 (int x, int y, int & sum, int & product) { sum=x+y; product=x*y; }; Then we’ll figure out the compiled code is just the same as in pointers example (9): Listing 29.20: Optimizing MSVC 2010 _x$ = 8 ; size = 4 _y$ = 12 ; size = 4 _sum$ = 16 ; size = 4 _product$ = 20 ; size = 4 ?f2@@YAXHHAAH0@Z PROC ; f2 mov ecx, DWORD PTR _y$[esp-4] mov eax, DWORD PTR _x$[esp-4] lea edx, DWORD PTR [eax+ecx] imul eax, ecx mov ecx, DWORD PTR _product$[esp-4] push esi mov esi, DWORD PTR _sum$[esp] mov DWORD PTR [esi], edx mov DWORD PTR [ecx], eax pop esi ret 0 ?f2@@YAXHHAAH0@Z ENDP ; f2 (A reason why C++ functions has such strange names, is described here: 29.1.1.) 29.4 STL N.B.: all examples here were checked only in 32-bit environment. x64 wasn’t checked. 29.4.1 std::string Internals Many string libraries ( [37, 2.2]) implements structure containing pointer to the buer containing string, a variable always containing current string length (that is very convenient for many functions: [37, 2.2.1]) and a variable containing current buer size. A string in buer is usually terminated with zero: in order to be able to pass a pointer to a buer into the functions taking usual C ASCIIZ-string. It is not specified in the C++ standard ( [16]) how std::string should be implemented, however, it is usually implemented as described above. 261 29.4. STL CHAPTER 29. C++ By standard, std::string is not a class (as QString in Qt, for instance) but template, this is done in order to support various character types: at least char and wchar_t. There are no assembly listings, because std::string internals in MSVC and GCC can be illustrated without them. MSVC MSVC implementation may store buer in place instead of pointer to buer (if the string is shorter than 16 symbols). This mean that short string will occupy at least 16 + 4 + 4 = 24 bytes in 32-bit environment or at least 16 + 8 + 8 = 32 bytes in 64-bit, and if the string is longer than 16 characters, add also length of the string itself. Listing 29.21: example for MSVC #include #include struct std_string { union { char buf[16]; char* ptr; } u; size_t size; // AKA ’Mysize’ in MSVC size_t capacity; // AKA ’Myres’ in MSVC }; void dump_std_string(std::string s) { struct std_string *p=(struct std_string*)&s; printf ("[%s] size:%d capacity:%d\n", p->size>16 ? p->u.ptr : p->u.buf, p->size, p->⤦ Ç capacity); }; int main() { std::string s1="short string"; std::string s2="string longer that 16 bytes"; dump_std_string(s1); dump_std_string(s2); // that works without using c_str() printf ("%s\n", &s1); printf ("%s\n", s2); }; Almost everything is clear from the source code. Couple notes: If the string is shorter than 16 symbols, a buer for the string will not be allocated in the heap. This is convenient because in practice, large amount of strings are short indeed. Apparently, Microso developers chose 16 characters as a good balance. Very important thing here is in the end of main() functions: I’m not using c_str() method, nevertheless, if to compile the code and run, both strings will be appeared in the console! This is why it works. The string is shorter than 16 characters and buer with the string is located in the beginning of std::string object (it can be treated just as structure). printf() treats pointer as a pointer to the null-terminated array of characters, hence it works. Second string (longer than 16 characters) printing is even more dangerous: it is typical programmer’s mistake (or typo) to forget to write c_str(). This works because at the moment a pointer to buer is located at the start of structure. This may le unnoticed for a long span of time: until a longer string will appear there, then a process will crash. GCC GCC implementation of a structure has one more variable—reference count. One interesting fact is that a pointer to std::string instance of class points not to beginning of the structure, but to the pointer to buer. In libstdc++-v3\include\bits\basic_string.h we may read that it was made for convenient debugging: * The reason you want _M_data pointing to the character %array and 262 29.4. STL CHAPTER 29. C++ * not the _Rep is so that the debugger can see the string * contents. (Probably we should add a non-inline member to get * the _Rep for the debugger to use, so users can check the actual * string length.) basic_string.h source code I considering this in my example: Listing 29.22: example for GCC #include #include struct std_string { size_t length; size_t capacity; size_t refcount; }; void dump_std_string(std::string s) { char *p1=*(char**)&s; // GCC type checking workaround struct std_string *p2=(struct std_string*)(p1-sizeof(struct std_string)); printf ("[%s] size:%d capacity:%d\n", p1, p2->length, p2->capacity); }; int main() { std::string s1="short string"; std::string s2="string longer that 16 bytes"; dump_std_string(s1); dump_std_string(s2); // GCC type checking workaround: printf ("%s\n", *(char**)&s1); printf ("%s\n", *(char**)&s2); }; A trickery should be also used to imitate mistake I already wrote above because GCC has stronger type checking, never- theless, printf() works here without c_str() as well. More complex example #include #include int main() { std::string s1="Hello, "; std::string s2="world!\n"; std::string s3=s1+s2; printf ("%s\n", s3.c_str()); } Listing 29.23: MSVC 2012 $SG39512 DB ’Hello, ’, 00H $SG39514 DB ’world!’, 0aH, 00H $SG39581 DB ’%s’, 0aH, 00H 263 29.4. STL CHAPTER 29. C++ _s2$ = -72 ; size = 24 _s3$ = -48 ; size = 24 _s1$ = -24 ; size = 24 _main PROC sub esp, 72 push 7 push OFFSET $SG39512 lea ecx, DWORD PTR _s1$[esp+80] mov DWORD PTR _s1$[esp+100], 15 mov DWORD PTR _s1$[esp+96], 0 mov BYTE PTR _s1$[esp+80], 0 call ?assign@?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAEAAV12@PBDI@Z ;⤦ Ç std::basic_string,std::allocator >::assign push 7 push OFFSET $SG39514 lea ecx, DWORD PTR _s2$[esp+80] mov DWORD PTR _s2$[esp+100], 15 mov DWORD PTR _s2$[esp+96], 0 mov BYTE PTR _s2$[esp+80], 0 call ?assign@?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAEAAV12@PBDI@Z ;⤦ Ç std::basic_string,std::allocator >::assign lea eax, DWORD PTR _s2$[esp+72] push eax lea eax, DWORD PTR _s1$[esp+76] push eax lea eax, DWORD PTR _s3$[esp+80] push eax call ??$?HDU?$char_traits@D@std@@V?$allocator@D@1@@std@@YA?AV?$basic_string@DU?⤦ Ç $char_traits@D@std@@V?$allocator@D@2@@0@ABV10@0@Z ; std::operator+,std::allocator > ; inlined c_str() method: cmp DWORD PTR _s3$[esp+104], 16 lea eax, DWORD PTR _s3$[esp+84] cmovae eax, DWORD PTR _s3$[esp+84] push eax push OFFSET $SG39581 call _printf add esp, 20 cmp DWORD PTR _s3$[esp+92], 16 jb SHORT $LN119@main push DWORD PTR _s3$[esp+72] call ??3@YAXPAX@Z ; operator delete add esp, 4 $LN119@main: cmp DWORD PTR _s2$[esp+92], 16 mov DWORD PTR _s3$[esp+92], 15 mov DWORD PTR _s3$[esp+88], 0 mov BYTE PTR _s3$[esp+72], 0 jb SHORT $LN151@main push DWORD PTR _s2$[esp+72] call ??3@YAXPAX@Z ; operator delete add esp, 4 $LN151@main: cmp DWORD PTR _s1$[esp+92], 16 264 29.4. STL CHAPTER 29. C++ mov DWORD PTR _s2$[esp+92], 15 mov DWORD PTR _s2$[esp+88], 0 mov BYTE PTR _s2$[esp+72], 0 jb SHORT $LN195@main push DWORD PTR _s1$[esp+72] call ??3@YAXPAX@Z ; operator delete add esp, 4 $LN195@main: xor eax, eax add esp, 72 ret 0 _main ENDP Compiler not constructing strings statically: how it is possible anyway if buer should be located in the heap? Usual ASCIIZ strings are stored in the data segment instead, and later, at the moment of execution, with the help of “assign” method, s1 and s2 strings are constructed. With the help of operator+, s3 string is constructed. Please note that there are no call to c_str() method, because, its code is tiny enough so compiler inlined it right here: if the string is shorter than 16 characters, a pointer to buer is leaved in EAX register, and an address of the string buer located in the heap is fetched otherwise. Next, we see calls to the 3 destructors, and they are called if string is longer than 16 characters: then a buers in the heap should be freed. Otherwise, since all three std::string objects are stored in the stack, they are freed automatically, upon function finish. As a consequence, short strings processing is faster because of lesser heap accesses. GCC code is even simpler (because GCC way, as I mentioned above, is not to store shorter string right in the structure): Listing 29.24: GCC 4.8.1 .LC0: .string "Hello, " .LC1: .string "world!\n" main: push ebp mov ebp, esp push edi push esi push ebx and esp, -16 sub esp, 32 lea ebx, [esp+28] lea edi, [esp+20] mov DWORD PTR [esp+8], ebx lea esi, [esp+24] mov DWORD PTR [esp+4], OFFSET FLAT:.LC0 mov DWORD PTR [esp], edi call _ZNSsC1EPKcRKSaIcE mov DWORD PTR [esp+8], ebx mov DWORD PTR [esp+4], OFFSET FLAT:.LC1 mov DWORD PTR [esp], esi call _ZNSsC1EPKcRKSaIcE mov DWORD PTR [esp+4], edi mov DWORD PTR [esp], ebx call _ZNSsC1ERKSs mov DWORD PTR [esp+4], esi mov DWORD PTR [esp], ebx 265 29.4. STL CHAPTER 29. C++ call _ZNSs6appendERKSs ; inlined c_str(): mov eax, DWORD PTR [esp+28] mov DWORD PTR [esp], eax call puts mov eax, DWORD PTR [esp+28] lea ebx, [esp+19] mov DWORD PTR [esp+4], ebx sub eax, 12 mov DWORD PTR [esp], eax call _ZNSs4_Rep10_M_disposeERKSaIcE mov eax, DWORD PTR [esp+24] mov DWORD PTR [esp+4], ebx sub eax, 12 mov DWORD PTR [esp], eax call _ZNSs4_Rep10_M_disposeERKSaIcE mov eax, DWORD PTR [esp+20] mov DWORD PTR [esp+4], ebx sub eax, 12 mov DWORD PTR [esp], eax call _ZNSs4_Rep10_M_disposeERKSaIcE lea esp, [ebp-12] xor eax, eax pop ebx pop esi pop edi pop ebp ret It can be seen that not a pointer to object is passed to destructors, but rather a place 12 bytes (or 3 words) before, i.e., pointer to the real start of the structure. std::string as a global variable Experienced C++ programmers may argue: a global variables of STL7 types are in fact can be defined. Yes, indeed: #include #include std::string s="a string"; int main() { printf ("%s\n", s.c_str()); }; Listing 29.25: MSVC 2012 $SG39512 DB ’a string’, 00H $SG39519 DB ’%s’, 0aH, 00H _main PROC cmp DWORD PTR ?s@@3V?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@A+20, 16 mov eax, OFFSET ?s@@3V?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@A ; s cmovae eax, DWORD PTR ?s@@3V?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@A push eax push OFFSET $SG39519 ; ’%s’ 7(C++) Standard Template Library: 29.4 266 29.4. STL CHAPTER 29. C++ call _printf add esp, 8 xor eax, eax ret 0 _main ENDP ??__Es@@YAXXZ PROC ; ‘dynamic initializer for ’s’’, COMDAT push 8 push OFFSET $SG39512 ; ’a string’ mov ecx, OFFSET ?s@@3V?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@A ; s call ?assign@?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@QAEAAV12@PBDI@Z ;⤦ Ç std::basic_string,std::allocator >::assign push OFFSET ??__Fs@@YAXXZ ; ‘dynamic atexit destructor for ’s’’ call _atexit pop ecx ret 0 ??__Es@@YAXXZ ENDP ; ‘dynamic initializer for ’s’’ ??__Fs@@YAXXZ PROC ; ‘dynamic atexit destructor for ’s’’, COMDAT push ecx cmp DWORD PTR ?s@@3V?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@A+20, 16 jb SHORT $LN23@dynamic push esi mov esi, DWORD PTR ?s@@3V?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@A lea ecx, DWORD PTR $T2[esp+8] call ??0?$_Wrap_alloc@V?$allocator@D@std@@@std@@QAE@XZ ; std::_Wrap_alloc >::_Wrap_alloc > push OFFSET ?s@@3V?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@A ; s lea ecx, DWORD PTR $T2[esp+12] call ??$destroy@PAD@?$_Wrap_alloc@V?$allocator@D@std@@@std@@QAEXPAPAD@Z ; std::_Wrap_alloc<⤦ Ç std::allocator >::destroy lea ecx, DWORD PTR $T1[esp+8] call ??0?$_Wrap_alloc@V?$allocator@D@std@@@std@@QAE@XZ ; std::_Wrap_alloc >::_Wrap_alloc > push esi call ??3@YAXPAX@Z ; operator delete add esp, 4 pop esi $LN23@dynamic: mov DWORD PTR ?s@@3V?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@A+20, 15 mov DWORD PTR ?s@@3V?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@A+16, 0 mov BYTE PTR ?s@@3V?$basic_string@DU?$char_traits@D@std@@V?$allocator@D@2@@std@@A, 0 pop ecx ret 0 ??__Fs@@YAXXZ ENDP ; ‘dynamic atexit destructor for ’s’’ In fact, a special function with all constructors of global variables is called from CRT, before main(). More than that: with the help of atexit() another function is registered: which contain all destructors of such variables. GCC works likewise: Listing 29.26: GCC 4.8.1 main: push ebp mov ebp, esp and esp, -16 sub esp, 16 mov eax, DWORD PTR s mov DWORD PTR [esp], eax call puts xor eax, eax leave 267 29.4. STL CHAPTER 29. C++ ret .LC0: .string "a string" _GLOBAL__sub_I_s: sub esp, 44 lea eax, [esp+31] mov DWORD PTR [esp+8], eax mov DWORD PTR [esp+4], OFFSET FLAT:.LC0 mov DWORD PTR [esp], OFFSET FLAT:s call _ZNSsC1EPKcRKSaIcE mov DWORD PTR [esp+8], OFFSET FLAT:__dso_handle mov DWORD PTR [esp+4], OFFSET FLAT:s mov DWORD PTR [esp], OFFSET FLAT:_ZNSsD1Ev call __cxa_atexit add esp, 44 ret .LFE645: .size _GLOBAL__sub_I_s, .-_GLOBAL__sub_I_s .section .init_array,"aw" .align 4 .long _GLOBAL__sub_I_s .globl s .bss .align 4 .type s, @object .size s, 4 s: .zero 4 .hidden __dso_handle It even not creates separated functions for this, each destructor is passed to atexit(), one by one. 29.4.2 std::list This is a well-known doubly-linked list: each element has two pointers, to the previous and the next elements. This mean that a memory footprint is enlarged by 2 words for each element (8 bytes in 32-bit environment or 16 bytes in 64-bit). This is also a circular list, meaning that the last element has a pointer to the first and vice versa: first element has a pointer to the last one. C++ STL just append “next” and “previous” pointers to your existing structure you wish to unite into a list. Let’s work out an example with a simple 2-variable structure we want to store in the list. Although standard C++ standard [16] does not oer how to implement it, MSVC and GCC implementations are straight- forward and similar to each other, so here is only one source code for both: #include #include
- #include