ARM and Thumb-2 Instruction Set Quick Reference Card



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ARM® and Thumb®-2 Instruction Set Quick Reference Card Key to Tables Rm {, } See Table Register, optionally shifted by constant See Table Flexible Operand 2. Shift and rotate are only available as part of Operand2. A comma-separated list of registers, enclosed in braces { and }. See Table PSR fields. As , must not include the PC. Either CPSR (Current Processor Status Register) or SPSR (Saved Processor Status Register) As , including the PC. C*, V* Flag is unpredictable in Architecture v4 and earlier, unchanged in Architecture v5 and later. +/- + or –. (+ may be omitted.) Can be Rs or an immediate shift value. The values allowed for each shift type are the same as those § See Table ARM architecture versions. shown in Table Register, optionally shifted by constant. Interrupt flags. One or more of a, i, f (abort, interrupt, fast interrupt). x,y B meaning half-register [15:0], or T meaning [31:16]. See Table Processor Modes ARM: a 32-bit constant, formed by right-rotating an 8-bit value by an even number of bits. SPm SP for the processor mode specified by Thumb: a 32-bit constant, formed by left-shifting an 8-bit value by any number of bits, or a bit Least significant bit of bitfield. pattern of one of the forms 0xXYXYXYXY, 0x00XY00XY or 0xXY00XY00. Width of bitfield. + must be <= 32. See Table Prefixes for Parallel instructions {X} RsX is Rs rotated 16 bits if X present. Otherwise, RsX is Rs. {IA|IB|DA|DB} Increment After, Increment Before, Decrement After, or Decrement Before. {!} Updates base register after data transfer if ! present (pre-indexed). IB and DA are not available in Thumb state. If omitted, defaults to IA. {S} Updates condition flags if S present. B, SB, H, or SH, meaning Byte, Signed Byte, Halfword, and Signed Halfword respectively. {T} User mode privilege if T present. SB and SH are not available in STR instructions. {R} Rounds result to nearest if R present, otherwise truncates result. Operation § Assembler S updates Action Notes Add Add ADD{S} Rd, Rn, N Z C V Rd := Rn + Operand2 N with carry ADC{S} Rd, Rn, N Z C V Rd := Rn + Operand2 + Carry N wide T2 ADD Rd, Rn, # Rd := Rn + imm12, imm12 range 0-4095 T, P saturating {doubled} 5E Q{D}ADD Rd, Rm, Rn Rd := SAT(Rm + Rn) doubled: Rd := SAT(Rm + SAT(Rn * 2)) Q Address Form PC-relative address ADR Rd,



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